Driver circuit, driver apparatus, and image forming apparatus

ABSTRACT

A driver circuit drives a plurality of groups of light emitting elements. Each element includes an anode, a cathode connected to the ground, and a gate that controls electrical conduction between the anode and cathode. A first driver section simultaneously drives the anodes of the elements of the plurality of groups of elements. A second driver section simultaneously drives the gates of the elements in a corresponding group of the plurality of groups. The second driver section includes a series connection of a first switch element and a voltage level shifter. The series connection is connected between a power supply and the group of gates. The second driver section further includes a second switch element connected between the group of gates and the ground.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a driver circuit for cyclicallyselectively driving a row of a plurality of elements, e.g., lightemitting thyristors as a light source for an electrophotographicprinter, a driving apparatus that employs the driver circuit, and animage forming apparatus that employs the driving apparatus.

Some existing image forming apparatus such as an electrophotographicprinter employ an exposing unit that includes a plurality of lightemitting elements. The light emitting elements include light emittingdiodes (LEDs), an organic electroluminescence (organic EL), and lightemitting thyristors.

An exposing unit using LEDs includes a driver circuit for acorresponding LED or a driver circuit for a group of LEDs. The LED turnson to emit light when current flows from anode to cathode of the LED andturns off when current does not flow. The light output of an LED dependson the drive current therethrough, and can be controlled by adjustingthe drive current.

A well known configuration of the driver circuit is such that MOStransistors are operated in their saturation region to perform aconstant current function.

Another well known driver circuit includes an anode driver circuit and acathode driver circuit, and is employed in an optical print head usinglight emitting thyristors. One such driver circuit is disclosed inJapanese Patent Application Laid-Open No. 08-153890. Light emittingthyristors are of N type conductivity gate configuration ofsemiconductor layers of a PNPN structure which includes a first layer oran anode of P-type conductivity, a second layer or a gate terminal of anN-type conductivity type, and a fourth layer or a cathode of an N-typeconductivity. A plurality of groups of light emitting thyristors aredriven in a time division manner, each group including a plurality oflight emitting thyristors which are aligned side by side and have theiranodes connected together and their gates connected together.

Existing driver circuits and driving apparatus suffer from the followingdrawbacks. When a group of light emitting thyristors are driven in atime division manner, the gates of selected light emitting thyristorsare set to the Low level and those of non-selected light emittingthyristors are set to the High level.

The driver ICs for driving the group of thyristors are monolithic ICsmanufactured by a CMOS transistor process, and operate at a supplyvoltage of 5 volts. An existing driver circuit applies a logic signal ofthe H level, which is substantially equal to the supply voltage of 5 V,to the gate of the light emitting thyristor. Light emitting thyristorssustain a voltage of only about 7 V, which has not a sufficient marginagainst the supply voltage of 5 V. Thus, the gate voltage of the H levelmay break down the thyristor.

A reverse gate voltage is applied across the second layer (N-type layer)and the third layer (P-type layer) of the light emitting thyristor. Thereverse breakdown voltage of a PN junction is known to be about 15volts. The gate-to-cathode sustaining voltage of the thyristor is equalto a collector sustaining voltage Vceo(max) of an NPN transistor asfollows: Vceo(max)=BV/β^(1/n) where BV is the reverse breakdown voltageof a PN reverse junction, β is the current amplification factor of anNPN transistor, and n is an empirical coefficient in the range of 3 to6. The light emitting thyristors have a sustaining voltage of only about7 V, which is not a sufficient margin relative to the supply voltage of5 V. Thus, the gate voltage of the H level may cause breakdown of thethyristors.

For gallium arsenide, GaAs, the value of Vceo(max) is obtained asfollows:

Vceo(max)=15/50^(1/6)=7.8 V

where is β=50, n=6, and BV is 15 V.

A Vceo(max) of 7.8 V may not have a sufficient voltage margin relativeto a common power supply voltage of 5 V at which driver circuitsoperate. An insufficient Vceo (max) may cause problems such as breakdownof light emitting thyristors and deterioration of light emittingthyristors due to application of 5 V for a long period of time. Suchdeterioration of thyristors includes fluctuation in light output anddecreased switching speed resulting from deterioration of currentamplification.

In order to improve the switching speed of light emitting thyristors,the current amplification of NPN transistors needs to be increased.However, increasing current amplification will deteriorate Vceo (max).This implies that the reverse breakdown voltage of a PN junction cannotbe increased independently of Vceo(max). In other words, switching speedand Vceo(max) are two opposing factors. Thus, there is a need for a goodsolution.

SUMMARY OF THE INVENTION

An object of the invention is to solve the aforementioned prior artproblems and to provide

A driver circuit drives a plurality of groups of light emittingelements. Each element includes an anode, a cathode connected to theground, and a gate that controls electrical conduction between the anodeand cathode. A first driver section simultaneously drives the anodes ofthe elements of the plurality of groups of elements. A second driversection simultaneously drives the gates of the elements in acorresponding group of the plurality of groups. The second driversection includes a series connection of a first switch element and avoltage level shifter. The series connection is connected between apower supply and the group of gates. The second driver section furtherincludes a second switch element connected between the group of gatesand the ground.

A driver circuit drives a plurality of groups of light emittingelements. Each element includes an anode, a cathode connected to theground, and a gate that controls electrical conduction between the anodeand cathode. A first driver section drives simultaneously firstterminals of the elements of the plurality of groups of elements. Asecond driver section simultaneously drives third terminals of elementsin a corresponding group of the plurality of groups. The second driversection includes a first switch element connected between a second nodeat a second potential and the group of third terminals. The seconddriver section further includes a second switch element connectedbetween the third terminals and the first node, the second switchelement having a different conductivity type from the first switchelement.

A driver circuit for driving a plurality of groups of elements, eachelement including a first terminal, a second terminal connected to afirst node at a first potential, and a third terminal that controlselectrical conduction between the first terminal and the secondterminal. A first driver section simultaneously drives first terminalsof the elements of the plurality of groups of elements. A second driversection simultaneously drives third terminals of elements in acorresponding group of the plurality of groups. The second driversection includes a series connection of a first switch element and aforward-biased diode, the series circuit being connected between asecond node at a second potential and the group of third terminals. Thesecond driver section further including a second switch elementconnected between the third terminals and the first node, the secondswitch element being of a common conductivity type to the first switchelement.

Further scope of applicability of the present invention will becomeapparent from the detailed description given hereinafter. However, itshould be understood that the detailed description and specificexamples, while indicating preferred embodiments of the invention, aregiven by way of illustration only, since various changes andmodifications within the scope of the invention will become apparent tothose skilled in the art from this detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description given hereinbelow and the accompanying drawingswhich are given by way of illustration only, and thus are not limitingthe present invention, and wherein:

FIG. 1 illustrates the outline of an image forming apparatus accordingto a first embodiment;

FIG. 2 is a cross-sectional view of the optical print head 13 shown inFIG. 1;

FIG. 3 is a perspective view of the head circuit board shown in FIG. 2;

FIG. 4 is a block diagram illustrating the configuration of a printercontroller for use with the image forming apparatus 1 shown in FIG. 1;

FIG. 5 illustrates the circuit configuration of the optical print head13 shown in FIG. 4;

FIG. 6A illustrates the symbol of the thyristor;

FIG. 6B is a cross-sectional view of the thyristor;

FIG. 6C is a cross-sectional view of another structure of the lightemitting thyristor;

FIG. 6D is an equivalent circuit of the thyristors shown in FIGS. 6B and6C;

FIG. 7 is a block diagram illustrating the details of one of the driverICs 100-1, 100-2, . . . 100-26 shown in FIG. 5;

FIG. 8 is a schematic diagram illustrating, by way of example, theconfiguration of the sub memory circuit shown in FIG. 7;

FIG. 9 illustrates the configuration of the multiplexer 161 shown inFIG. 7;

FIG. 10 is a schematic diagram of the driver shown in FIG. 7;

FIG. 11 is a schematic diagram illustrating the configuration of thememory controller shown in FIG. 7;

FIG. 12 a schematic diagram illustrating the configuration of the signalselector shown in FIG. 7;

FIG. 13 illustrates the configuration of the control voltage generatorshown in FIG. 7;

FIGS. 14A and 14B illustrate the configuration of the first and secondgate drivers shown in FIG. 7;

FIG. 15 illustrates a gate driver 162A as a comparative example;

FIG. 16 is a timing chart illustrating the transferring of thecorrection data performed in the optical print head 13 after power-up ofthe image forming apparatus 1 of the first embodiment;

FIG. 17 illustrates the details of portions A and B shown in FIG. 16;

FIG. 18 illustrates the details of portions C and D shown in FIG. 16;

FIG. 19 illustrates the details of portions E and F shown in FIG. 16;

FIG. 20 illustrates the details of portions G and H;

FIGS. 21A and 21B illustrate the first and second gate drivers 162 and163 shown in FIG. 7 for driving the gates of the light emittingthyristor;

FIG. 21C illustrates changes in the gate current drawn to the same scaleof the gate current Ig;

FIG. 21D illustrates changes in the gate current drawn to the same scaleof the anode current as in FIGS. 21C;

FIG. 21E illustrate changes in the date-cathode voltage Vgk with theanode current of the light emitting thyristor.

FIG. 22A is a simple model representation illustrating only two lightemitting thyristors shown in FIG. 5;

FIG. 22B is a timing chart illustrating the operation of the lightemitting thyristors shown in FIG. 22A.

FIG. 23 is a schematic diagram illustrating a first gate driver 162Bwhich is a modification to the first gate driver 162 shown in FIG. 14B.

FIG. 24 is a schematic diagram illustrating a first gate driver 162Cwhich is a modification to the first gate driver 162 shown in FIG. 14B;

FIG. 25A is a schematic diagram illustrating the gate driver;

FIG. 25B is a top view illustrating the configuration of an NPNtransistor shown in FIG. 25A;

FIG. 25C is a cross-sectional view of the gate driver taken along a line25C-25C in FIG. 25B;

FIG. 26 is a timing chart illustrating the operation of two adjacentlight emitting thyristors shown in FIG. 22A when the two gate driversare used;

FIG. 27 is a schematic diagram illustrating a modification to the gatedriver shown in FIG. 25; and

FIG. 28 is a schematic diagram of the gate driver which is amodification to the gate driver of FIG. 25.

DETAILED DESCRIPTION OF THE INVENTION {Outline of Image FormingApparatus}

FIG. 1 illustrates the outline of an image forming apparatus accordingto a first embodiment.

The image forming apparatus 1 is an electrophotographic color printerthat employs a driver apparatus, e.g., an optical print head for drivinglight emitting elements, e.g., three-terminal thyristors. The imageforming apparatus 1 includes four process units 10-1 to 10-4 that formblack (K), yellow (Y), magenta (M), and cyan (C) images, respectively.The four process units are aligned from upstream to downstream of atransport path of a recording medium, e.g., paper 20. Each of theprocess units may be substantially identical; for simplicity only theoperation of the process unit 10-3 for forming cyan images will bedescribed, it being understood that the other process units may work ina similar fashion.

The process unit 10-3 includes a photoconductive drum 11 rotatable in adirection shown by arrow A. A charging unit 12, an exposing unit, e.g.,an optical print head 13, a developing unit 14, and a cleaning device 15are disposed in this order around the photoconductive drum 11. Thecharging unit 12 charges the surface of the photoconductive drum 11. Theexposing unit 13 selectively illuminates the charged surface of thephotoconductive drum 11 to form an electrostatic latent image. Thedeveloping unit 14 deposits magenta toner to the electrostatic latentimage formed on the photoconductive drum 11 to form a toner image. Thecleaning device 15 removes toner remaining on the photoconductive drum11 after transferring the toner image onto the paper 20. A drive source(not shown) drives the photoconductive drum 11 and a variety of rollersin rotation via a gear train.

A paper cassette 21, which holds a stack of paper 20 therein, isdisposed at a lower portion of the image forming apparatus 1. A hoppingroller 22 is disposed over the paper cassette 21, and feeds the paper 20on a sheet-by-sheet basis into the transport path. A discharge roller 25cooperates with pinch rollers 23 and 24 to hold the paper 20 in asandwiched relation. A registry roller 26 corrects the skew of the paper20, and transports the paper 20 to the process unit 10-1. The dischargeroller 25 and registry roller 26 are disposed downstream of the hoppingroller 22. A drive source (not shown) drives the hopping roller 22,discharge roller 25, and registry roller 26 in rotation via a geartrain.

Transfer units 27 are formed of, for example, a semi-conductive rubbermaterial, and parallel the photoconductive drums 11 of the process units10-1 to 10-4. When the toner images formed on the photoconductive drums11 are transferred onto the paper 20, the transfer units 27 receivevoltages so as to create a potential difference across each transferunit 27 and the surface of a corresponding photoconductive drum 11.

A fixing unit 28 is located downstream of the process unit 10-4, andincludes a heat roller, which incorporates a heater therein, and apressure roller. When the paper 20 passes through the gap between thepressure roller and the heat roller, the toner image on the paper 20 isfixed under heat and pressure. Discharge rollers 29 and 30, dischargepinch rollers 31 and 32, and a paper stacker 33 are disposed downstreamof the fixing unit 28. The discharge rollers 29 and 30 cooperate withthe pressure roller to hold the paper 20 in a sandwiched relation, andtransport the paper 20 to the paper stacker 33. The heat roller,pressure roller, and discharge rollers 29 and 30 are driven in rotationby a drive power transmitted via, for example, a gear train from a drivesource (not shown).

The image forming apparatus 1 operates as follows:

The hopping roller 22 feeds the paper 20 into the transport path fromthe paper cassette 21 on a sheet-by-sheet basis. The paper 20 is held bya transport roller 25, a registry roller 26, and pinch rollers 23 and 24in a sandwiched relation, and is transported into a transfer pointdefined between the photoconductive drum 11 of the process unit 10-1 andthe transfer unit 27. As the photoconductive drum 11 rotates, the paper20 is further transported through the transfer point so that the tonerimage on the photoconductive drum 11 is transferred onto the paper 20.Likewise, the paper 20 is transported through the remaining processunits 10-2 to 10-4 so that the toner images of corresponding colors aretransferred onto the paper 20 in registration.

When the paper 20 passes through the fixing unit 28, the toner imagescarried on the paper 20 are fixed. The paper 20 is further transportedby the discharge rollers 29 and 30 and pinch rollers 31 and 32 to thepaper stacker 33 defined on the outer wall of the image formingapparatus 1. This completes printing.

{Construction of Optical Print Head}

FIG. 2 is a cross-sectional view of the optical print head 13 shown inFIG. 1.

The optical print head 13 includes a base 13 a and a printed wiringboard 13 b fixed on the base 13 a. The printed wiring board 13 b carriesa plurality of driver circuits 100 (e.g., driver ICs at the bare chiplevel) mounted by means of, for example, thermosetting resin. Aplurality of arrays 200 of light emitting elements (e.g., light emittingthyristors) are disposed on the driver ICs 100. A rod lens array 13 c,which incorporates a plurality of columns of optical elements, islocated over the driver ICs. The rod lens array 13 c is fixedlysupported by a holder 13 d. Clamp members 13 e and 13 f firmly hold thebase 13 a, printed wiring board 13 b, and holder 13 d together.

{Head Circuit Board Unit}

FIG. 3 is a perspective view of the head circuit board shown in FIG. 2.The printed wiring board 13 b carries thereon a plurality of lightemitting thyristor arrays 200 at the bare chip level. The driver ICs 100are electrically connected to the light emitting thyristors by means ofthin film wirings. The driver ICs 100 and light emitting thyristorarrays 200 constitute a composite chip incorporating light emittingelements and driver elements. The respective terminals of the driver ICare connected by means of bonding wires 13 g to wiring pads (not shown)formed on the print wiring board 13 b.

{Printer Controller}

FIG. 4 is a block diagram illustrating the configuration of a printercontroller for use with the image forming apparatus 1 shown in FIG. 1.

The printer controller includes a printing controller 40 located in aprinting section of the image forming apparatus 1. The printingcontroller 40 mainly includes a microprocessor, a read only memory(ROM), a random access memory (RAM), an input/output port, and a timer.The printer controller receives a control signal SG1 and a video signal(bit map data arranged in a straight line) SG2 from an image processingsection (not shown) to perform sequential control of the overalloperation of the image forming apparatus 1, thereby performing printing.The printing controller 40 is connected to the four optical print heads13 of the process units 10-1 to 10-4, a heater 28 a of the fixing unit28, drivers 41 and 43, an incoming paper sensor 45, an outgoing papersensor 46, a remaining paper sensor 47, a paper size sensor 48, a fixingunit temperature sensor 49, a high voltage charging power supply 50, anda high voltage transferring power supply 51. The driver 41 is connectedto a developing/transferring process motor (PM) 42. The driver 43 isconnected to a paper transporting motor (PM) 44. The high voltagecharging power supply 50 is connected to the developing unit 14. Thehigh voltage transferring power supply 51 is connected to transfer units27.

The printing controller operates as follows:

Upon reception of the control signals SG1 to command printing from theimage processing section, the printing controller 40 determines by meansof the temperature sensor 49 whether the heat roller in the fixing unit28 is in a usable temperature range. If the temperature is not withinthe usable temperature range, the printing controller 40 supplieselectric power to the heater 28 a to heat the heat roller to the usabletemperature. The printing controller 40 then causes the driver 41 torotate the developing/transfer process motor 42, and outputs a chargingsignal SGC to turn on the high voltage charging power supply 50, therebycharging the developing unit 14.

Then, the remaining paper sensor 47 detects whether the paper 20 ispresent in the paper cassette and the paper size sensor 48 detects thesize of the paper 20. Thus, the paper 20 of the right size is fed to thetransport path. The paper transporting motor 44 is coupled to aplanetary gear assembly and is adapted to rotate in the forward andreverse directions. Switching the rotation direction of the papertransporting motor 44 allows switching of the rotation directions of thetransport rollers 25, depending on the size of the paper 20.

When printing on one page of paper is started, the paper transportingmotor 44 is rotated in the reverse direction, thereby transporting thepaper 20 by a predetermined amount until the incoming paper sensor 45detects the paper 20. The paper transporting motor 44 is then rotated inthe forward direction to transport the paper 20 into a print engine ofthe image forming apparatus 1.

When the paper 20 reaches a position where printing can be performed,the printing controller 40 provides a timing signal SG3 including a mainscanning sync signal and a sub scanning sync signal to an imageprocessing section (not shown), and receives the video signal SG2. Thevideo signal SG2 is edited on a page-by-page basis in the imageprocessing section and is received by the print controller 40. The videosignal SG2 is transferred as print data signals HD-DATA3 to HD-DATA0 aresupplied to the respective optical print heads 13. Each of the opticalprint heads 13 incorporates a plurality of light emitting thyristors,each thyristor forming a dot or pixel of an image.

Upon reception of the video signal SG2 for one line, the printingcontroller 40 provides the latch signal HD-LOAD to the respectiveoptical print heads 13. In response to the latch signal HD-LOAD, therespective optical print heads 13 hold the print data signal HD-DATA.The printing controller 40 is adapted to perform printing of the printdata signals HD-DATA3 to HD-DATA0 held in the respective print heads 13while the printing controller 40 is receiving the next video signals SG2from the image processing section.

The printing controller 40 provides the clock signal HD-CLK, a mainscanning sync signal HD-HSYNC-N, and a print drive signal HD-STB-N tothe respective optical print heads 13. The clock signal HD-CLK is usedto send the print data signals HD-DATA3 to HD-DATA0 to the optical heads13.

The video signal SG2 is transmitted and received on a line-by-linebasis. The optical print head 13 illuminates the negatively chargedsurface of the photoconductive drum 11 to form an electrostatic latentimage formed of dots having increased potential due to exposure tolight. The toner is negatively charged in the developing unit 14 and isthen attracted to the dots formed on the photoconductive drum 11 by theCoulomb force, thereby forming a toner image.

The toner image on the photoconductive drum 11 is then transported tothe transfer point defined between the photoconductive drum 1 and thetransfer unit 27. A transfer signal SG4 causes the high voltage transferpower supply 51 to turn on to apply a positive voltage, therebytransferring the toner image onto the paper 20 as the paper 20 passesthrough the transfer point defined between the photoconductive drum 11and the transfer unit 27. The paper 20 carries the toner image thereonand passes through the fixing point defined between the heat roller andpressure roller of the fixing unit 28, so that the toner image is fixedunder heat and pressure. The paper 20 is then further transported pastthe outgoing paper sensor 46.

In response to the detection signals from the paper size sensor 48 andincoming paper sensor 45, the printing controller 40 causes the highvoltage transfer power supply 51 to turn on to apply the high voltage tothe transfer unit 27 while the paper 20 is passing the transfer pointdefined between the photoconductive drum 11 and the transfer unit 27.When the paper 20 has passed the outgoing paper sensor 46 aftercompletion of printing, the printing controller 40 causes the highvoltage charging power supply 50 to stop applying the high voltage tothe developing section 14, and the developing/transferring process motor42 to stop rotating. The above-described operation is repeated until theentire print data has been printed.

{Circuit of Optical Print Head}

FIG. 5 illustrates the circuit configuration of the optical print head13 shown in FIG. 4.

The optical print head 13 is capable of forming an electrostatic latentimage on the photoconductive drum at a resolution of, for example, 600dpi.

The optical print head 13 includes the printed wiring board 13 b (FIG.3) on which a plurality of driver ICs 100 (e.g., 26 driver ICs) arearranged. FIG. 5 shows only two driver ICs, i.e., driver ICs 100-1 and100-2 and corresponding light emitting thyristor arrays 200-1 and 200-2arranged on the driver ICs. Each driver IC drives a corresponding lightemitting thyristor array. A total of 4992 light emitting thyristors areemployed to form an electrostatic latent image having a total of 4992dots. Each thyristor array includes a total of 192 light emittingthyristors 211-1 to 211-96 and 212-1 to 212-96 whose cathodes areconnected to the ground terminal GND. The anodes of adjacent thyristors(e.g., thyristors 211-1 and 212-2) are connected together to acorresponding one of the drive current output terminals DO1 to DO96 ofthe driver IC 100 by means of their film wirings.

A total of 26 driver ICs 100 are of an identical configuration, and arecascaded.

Data input terminals DATAI3 to DATAI0 receive print data signalsHD-DATA3 to HD-DATA0. A latch signal terminal LOAD receives a latchsignal HD-LOAD. A CLK terminal receives a clock signal HD-CLK. A VREFterminal receives a reference voltage VREF. An STB terminal receives theprint drive signal HD-STB-N, which serves as a strobe signal. A VDDterminal receives a power supply voltage VDD. The ground terminal GND isconnected to the ground. A HSYNC terminal receives the main scanningsync signal HD-HSYNC-N. Output data terminals DATAO3 to DATAO0 outputthe data to the next stage driver IC. The drive current output terminalsDO1-DO96 supply drive currents to the anodes of the light emittingthyristors 210 in the light emitting thyristor arrays. A gate drivesignal terminal G1 outputs a gate drive signals that drives the gates ofodd-numbered light emitting thyristors 210 through a common wire 220 a.A gate drive signal terminal G2 outputs a gate drive signal that drivesthe gates of even-numbered light emitting thyristors 210 through acommon wire 220 b.

The reference voltage VREF is a reference voltage relative to which thedrive currents for driving the light emitting thyristors are set. Thereference voltage VREF is output from a reference voltage generatingcircuit (not shown) in the optical print head 13. When the lightemitting thyristors are driven in a time-division manner, the mainscanning sync signal HD-HSYNC-N is a sync signal that indicates whetherthe odd-numbered light emitting thyristors should be driven or theeven-numbered light emitting thyristors should be driven.

{Operation of Optical Print Head}

The operation of the optical print head 13 of the above-describedconfiguration shown in FIG. 5 will be described. The print data signalsHD-DATA3 to HD-DATA0 are outputted simultaneously on the clock signalsHD-CLK, and drive adjacent four light emitting thyristors for 4 pixels.For this operation, the print controller 40 shown in FIG. 4 outputs theprint data signals HD-DATA3 to HD-DATA0 to the data input terminalsDATAI3 to DATA0 of the first driver IC 100-1, and the clock signalsHD-CLK to the CLK terminals of all the driver ICs 100-1 to 100-26. Theprint data signals HD-DATA3 to HD-DATA0 are shifter through the driverICs on the clock signal. The print data is bit data for a total of 4992bits (i.e., 4992 dots): 2496 odd-numbered bits and 2496 even-numberedbits. The bit data for the odd-numbered dots is first shifted throughshift registers implemented with flip-flops in the driver ICs, and thenthe bit data for the even-numbered dots is shifted through the sameshift registers.

Next, the latch signal HD-LOAD is inputted to the latch signal terminalsLOAD of all the driver ICs 100, so that the bit data in the shiftregister is latched to the latch circuit in the form of flip-flops(FFs). The High levels of the bit data latched in the latch circuitdrive the light emitting thyristors 210, which are connected to thedrive current output terminals DO1, DO2, . . . terminals, to turn onupon the print drive signal HD-STB-N.

Referring to FIG. 5, the optical print head 13 incorporates a largenumber of light emitting thyristor arrays 200. Therefore, the variationof characteristics of the light emitting thyristors due to manufacturingerrors cause variations of light output among the arrays of lightemitting thyristors and also among light emitting thyristors in the samearray. This causes dots on the photoconductive drum to be formed bydifferent amount of energy.

This phenomenon causes the variations of dot size during development ofa toner image, leading to uneven print density. In order to solve theproblem, the drive currents flowing through the respective lightemitting thyristors are usually adjusted so that all the light emittingthyristors output a substantially equal amount of light. The driver ICs100 shown in FIG. 5 incorporate such a drive current adjusting circuit,which will be described later.

{Light Emitting Thyristor}

FIGS. 6A-6D illustrate the structures of the light emitting thyristor210 shown in FIG. 5.

FIG. 6A illustrates the symbol of the thyristor.

FIG. 6B is a cross-sectional view of the thyristor.

FIG. 6C is a cross-sectional view of another structure of the lightemitting thyristor.

FIG. 6D is an equivalent circuit of the thyristors shown in FIGS. 6B and6C.

Referring to FIG. 6A, the light emitting thyristor 210 includes an anodeA, a cathode K, and a gate G.

Referring to FIG. 6B, the light emitting thyristor 210 is fabricated byepitaxially growing a predetermined crystal on a GaAs wafer by knownmetal organic chemical vapor deposition (MO-CVD).

First, a predetermined sacrificial layer and a buffer layer (not shown)are grown epitaxially. A wafer of a three-layer structure is thenfabricated. The three-layer structure includes an N-type layer 213 thatcontains an N-type impurity, a P-type layer 212 that contains a P-typeimpurity, and an N-type layer 211 that contains an N-type impurity, inthis order. A P-type impurity region 214 is selectively formed in theuppermost N-type layer 211 by photolithography.

Grooves are formed in the wafer to define individual devices by dryetching. When dry etching is performed, a part of the N-type layer 213,which is the lowermost layer of the light emitting thyristor 210, isetched to expose. A metal wiring is formed on the exposed region to forma cathode K. The P-type impurity region 214 and N-type layer 211 arealso formed as an anode A and a gate G, respectively.

The light emitting thyristor 210 shown in FIG. 6C is fabricated byepitaxially growing a predetermined crystal on a GaAs wafer by MO-CVD.

First, a predetermined sacrificial layer and a buffer layer (not shown)are exitaxially grown. A wafer of a PNPN four-layer structure is thenfabricated. The four-layer structure includes an N-type layer 213 thatcontains an N-type impurity, a P-type layer 212 that contains a p-typeimpurity, an N-type layer 211 that contains an N-type impurity, and aP-type layer 215 that contains a P-type impurity in this order.

Grooves are formed in the wafer to define individual devices by dryetching. When dry etching is performed, a part of the N-type 213, whichis the lowest layer of the light emitting thyristor 210, is exposed.Likewise, a part of the P-type layer 215, which is the uppermost layer,is exposed. A metal wiring is formed on the exposed region of the P-typelayer 215 to form the anode A. At the same time, the gate G is formed onthe N-type layer 211.

As is clear from FIG. 6D, the light emitting thyristor 210 isconstituted of a PNP transistor 221 and an NPN transistor 222. Theemitter of the PNP transistor 221 corresponds to the anode A of thelight emitting thyristors 210 and the base of the PNP transistor 221corresponds to the gate G. The gate G is also connected to the collectorof the NPN transistor 222. The collector of the PNP transistor 221 isconnected to the base of the NPN transistor 222. The emitter of the PNPNtransistor 222 corresponds to the cathode K of the thyristor 210.

The light emitting thyristor 210 shown in FIGS. 7A-7D has an AlGaAslayer formed on a GaAs wafer. The thyristor 210 is not limited to thisconfiguration. The thyristor 210 may have a layer of GaP, GaAsP, orAlGaInP formed on the GaAs wafer or a GaN or AlGaN layer formed on asapphire substrate.

The thyristor 210 shown in FIGS. 6B and 6C may be bonded by epitaxiallybonding to a wafer on which a plurality of driver ICs 100 shown in FIG.5 are arranged, and then unnecessary portions are removed from the waferby a known etching technique to expose portions to be formed intoterminals of the light emitting thyristor 210. The film wirings areformed by photolithography to connect the terminals of the driver IC 100to the terminal areas of the light emitting thyristor 210. The wafer isthen diced into individual chips of driver ICs by a known dicingtechnique, thereby obtaining composite chips that include light emittingthyristors and driver elements.

{Overall Configuration of Driver ICs}

FIG. 7 is a block diagram illustrating the details of one of the driverICs 100-1, 100-2, . . . 100-26 shown in FIG. 5.

Each driver IC 100 includes a shift register 110 constituted of aplurality of cascaded flip flops FFs 111A1-111A25, FFs 111B1-111B25, FFs111C1-111C25, and FFs 111D1-111D25. The shift register 110 receives theprint data signals HD-DATA3 to HD-DATA0 at the data input terminalsDATAI3 to DATAI0 on the clock signals HD-CLK received at the clockterminal CLK, while also shifting the print data on the clock CLK.

The flip flops FFs 111A1-111A25 are cascaded and shift the data receivedat the data input terminal DATAI0. The data input terminal DATAI0 of thedriver IC 100 is connected to the data input terminal D of the flip flopFF 111A1. The data output terminals Q of the flip flops FFs 111A24 and111A25 are connected to the data input terminals A0 and B0 of ashift-stage selector 120, respectively. The output terminal Y0 of theshift-stage selector 120 is connected to a data output terminal DATAO0of the driver IC 100. Likewise, the flip flops FFs 111B1-111B25, FFs111C1-111C25, and FFs 111D1-111D25 are also cascaded. Data inputterminals DATAI1, DATAI2, and DATAI3 are connected to the data inputterminals D of the flip flops FFs 111B1, 111C1, and 111D1. The outputterminals Q of the FF111B24 and FF111B25 are connected to inputterminals A1 and B1 of the shift-stage selector 120, respectively. Theoutput terminals Q of the FF111C24 and FF111C25 are connected to inputterminals A2 and B2 of the shift-stage selector 120, respectively. Theoutput terminals Q of the flip flops FFs 111D24 and 111D25 are connectedto input terminals A3 and B3 of the shift-stage selector 120,respectively. The output terminals Y1, Y2, and Y3 of the shift-stageselector 120 are connected to data output terminals DATAO1, DATAO2, andDATAO3 of the driver IC 100, respectively.

Thus, the flip flops FFs 111A-111A25, FFs 111B1-111B25, FFs111C1-111C25, and FFs 111D1-111D25 constitute the 25-stage shiftregister 110. The shift-stage selector 120 enables switching of theshift register 110 between a 24-stage shift register mode and a 25-stageshift register mode. The data output terminals DATAO0 to DATAO3 of eachdriver IC 100 are connected to the data input terminals DATAI0 toDATAIO3 of the next driver IC 100 (FIG. 5). The above-described shiftregister 110 is a part of the shift register constituted of a total of26 driver ICs 100-1 to 100-26. Thus, for example, the print data signalHD-DATA3 is shifted either in the 24×26 stage shift register mode or inthe 25×26 stage shift register mode, and is finally loaded to a driver181-1 after completion of shifting.

The outputs of the shift register 110 are connected to the inputs of alatch circuit 130 and a memory circuit 150. The outputs of the latchcircuit 130 are connected to a driver section 180. A memory controller141 is connected to the input of the memory circuit 150 whose outputsare connected to a multiplexer 160. A signal selector 142 is connectedto the inputs of the multiplexer 160. The drive terminal STB of thedriver IC 100 is connected to a pull-up resistor 143 and an inverter144. An inverter 145 is connected to the latch signal terminal LOAD ofthe driver IC 100. The output terminals of the inverters 144 and 145 areconnected to the input terminals of a 2-input NAND gate 146 whose outputterminal is connected to inputs of the driver section 180. Controlvoltage receiving terminals V of the driver section 180 are connected toa control voltage generator 170.

The latch circuit 130 latches the output signals of the shift register110 on the latch signal LOAD-P (“P” denotes positive logic) received atthe latch signal terminal LOAD. The latch circuit 130 includes aplurality of sub latching elements 131A1-131A24, 131B1-131B24,131C1-131C24, and 131D1-131D24. Each sub latching element has a datainput terminal D, a latch signal input terminal G, and an inverted dataoutput terminal QN. The inverted data output terminals QN of thelatching elements are connected to the driver section 180.

The memory circuit 150 is controlled by the memory controller 141, andstores correction data for correcting the variations of the lightemitting thyristors. (i.e., dot correction data), correction data forcorrecting the variations of the light output of each of the respectivelight emitting thyristor arrays 200 (i.e., chip correction data), ordata unique to each of the respective drivers IC 100. The memory circuit150 includes a plurality of sub memory circuits 151A1-151A24,151B1-151B24, 151C1-151C24, and 151D1-151D24 and a sub memory circuit152. The outputs of the sub memory circuits 151A1-151A24, 151B1-151324,151C1-151C24, and 151D1-151D24 are connected to the multiplexer 160 andthe outputs of the sub memory circuit 152 are output to the controlvoltage generator 170. The sub memory circuits 151A1-151A24,151B1-151B24, 151C1-151C24, and 151D1-151D24 each have a data inputterminal D, memory cell selecting terminals W0-W3, write-enable signalinput terminals E1 and E2, and data output terminals EVN and ODD. Thesub memory circuit 152 has data input terminal D, memory cell selectingterminals W0-W3, a write-enable signal input terminal E1, and dataoutput terminals Q0-Q3. The outputs of the memory circuit 150 areconnected to the multiplexer 160 and the control voltage generator 170.

The memory controller 141, which controls the memory circuit 150, has alatch signal terminal LOAD, a drive signal input terminal STB, memorycell selecting signal terminals W0-W3, write-enable signal outputterminals E1 and E2. The memory controller 141 outputs memory cellselecting signal from the memory cell selecting signal terminals W0-W3and write-enable signal from the write-enable signal input terminals E1and E2 to the plurality of sub memory circuits 151A1-151A24,151B1-151B24, 151C1-151C24, and 151D1-151D24, and the sub memory circuit152.

The multiplexer 160 is controlled by the signal selector 142 to selecteither the correction data for the odd-numbered dots or the correctiondata for the even-numbered dots, the correction data being outputtedfrom the plurality of sub memory circuits 151A-151A24, 151B1-151B24,151C1-151C24, and 151D1-151D24. The multiplexer 160 includes a pluralityof sub multiplexers 161A1-161A24, 16131-161B24, 161C1-161C24, and161D1-161D24, each sub multiplexer having data input terminals EVN andODD, selection signal terminals S1N and S2N, data output terminalsQ0-Q3. The data output terminals Q0-Q3 of the sub multiplexers areconnected to the driver 180.

The signal selector 142, which controls the multiplexer 160, has themain scanning synch signal HSYNC terminal, latch signal terminal LOAD,and first and second selection signal terminals S1N and S2N. The signalselector 142 outputs a selection signal from the first selection signalterminal S1N to select the correction data for the odd-numbered and aselection signal from the second selection signal terminal S2N to selectthe correction data for the even-numbered dots. The first selectionsignal terminal S1N is connected to the gate drive signal terminal G1via a first gate driver 162 and the selection signal output terminal S2Nis connected to gate drive signal terminal G2 via a second gate driver163.

The control voltage generator 170 is connected to the inputs of thedriver section 180, and has data input terminals S0-S3, a referencevoltage input terminal VREF, and a control voltage output terminal V.The control voltage generator 170 receives the reference voltage VREFgenerated by, for example, a regulator circuit (not shown), andgenerates a control voltage Vcont for driving the light emittingthyristors. The control voltage V is supplied to the driver section 180.The control voltage generator 170 maintains the reference voltage VREFat a constant value even if the supply voltage VDD may momentarily dropsuch as when all of the LEDs are turned on. Thus, the thyristor drivecurrent may be kept unchanged.

The driver section 180 outputs drive currents through the drive currentoutput terminals DO01-DO96 for driving the light emitting thyristorarrays 200-1, 200-2, . . . , 200-26, the drive currents being generatedin accordance with the outputs of the latch circuit 130, NAND gate 146,multiplexer 160, and control voltage generator 170. The driver section180 includes drivers 181-1 to 181-96, each driver including data inputterminals Q0-Q3, a terminal E, signal input terminal S, and a controlvoltage input terminal V.

The NAND gate 146 is connected to the signal input terminals S of thedriver section 180, receives the print drive signal HD-STB-N and thelatch signal LOAD-P through the inverters 144 and 145, and then outputsa control signal that makes the driver section 180 on or off.

{Sub Memory Circuits}

Each of the sub memory circuits 151A1-151A24, 151B1-151B24,151C1-151C24, and 151D1-151D24 in the driver IC 100 shown in FIG. 7 maybe substantially identical.

FIG. 8 is a schematic diagram illustrating, by way of example, theconfiguration of the sub memory circuit 151A1 shown in FIG. 7.

The sub memory circuit, for example, 151A1 shown in FIG. 8 holds 4-bitdot correction data for odd and even numbered dots which can adjust thedrive current for a light emitting thyristor in 16 levels, therebycorrecting the light output of the light emitting thyristor.

The sub memory circuit 151A1 includes two adjacent, identical memorycell groups 300-1 and 300-2. The memory cell group 300-1 (e.g., dot #1)holds correction data for an odd-numbered dot and the memory cell 300-2(e.g., dot #2) holds correction data for an even-numbered dot. Eachmemory cell group includes 4 memory cells, e.g., 311-314, that hold the4-bit dot correction data for correcting the light output of the lightemitting thyristor. The 4-bit dot correction data is capable of settingthe thyristor drive current in 16 increments for each dot. Each of thememory cell groups 300-1 and 300-2 may be substantially identical; forsimplicity only the memory cell group 300-1 will be described, it beingunderstood that the memory cell group 300-2 may work in a similarfashion.

The correction data terminal D of the sub memory circuit 151A1 receivesthe correction data from the output terminal Q of the flip flop FF 111A1of the shift register 110. A write-enable signal output terminal E1receives a write-enable signal, which is outputted from the write-enablesignal output terminal E1 of the memory controller 141 and enableswriting of the data for odd-numbered dots. Another write-enable signaloutput terminal E2 receives another write-enable signal, which isoutputted from the write-enable signal output terminal E2 of the memorycontroller 141 and enables writing of the data for even-numbered dots.The memory cell selecting terminals W0-W3 receive memory cell selectingsignals from the memory cell selecting terminals W0-W3 of the memorycontroller 141. The terminals ODD0-ODD3 output the correction data forodd-numbered dots. The terminals EVN0-EVEN3 output the correction datafor the even-numbered dots.

The correction data terminal D is connected to the memory cell group300-1 via a buffer 301. The output of the buffer 301 is connected to theinput of an inverter 302 which in turn produces an inverted correctiondata, i.e., a logic inversion of the correction data.

The memory cell group 300-1 includes memory means (e.g., cells) 311 to314, data switching means (NMOS transistor switches 321 to 328), andanother data switching means (NMOS transistor switches 331 to 338).

The memory cell 311 includes first and second inverters 311 a and 311 bcascaded to form a ring circuit. In other words, the first inverter hasa first output terminal and a first input terminal, and the secondinverter having a second output terminal and a second input terminal.The first output terminal is connected to the second input and thesecond output is connected to the first input terminal. Likewise, thememory cell 312 includes inverters 312 a and 312 b cascaded to form aring. The memory cell 313 includes inverters 313 a and 313 b to form aring. The memory cell 314 includes inverters 314 a and 314 b to form aring. The supply terminals of the inverters 311 a, 311 b, 312 a, 312 b,313 a, 313 b, 314 a, and 314 b are connected to the supply terminal VDDto which power supply voltage VDD, e.g., 5 V, is applied.

The gates of NMOS transistors 321, 323, 325, and 327 are connected tothe enable signal terminal E1 while the gates of NMOS transistors 322,324, 326, and 328 are connected to the memory cell selecting terminalsW0, W1, W2, and W3, respectively. The output terminal of the buffer 301is connected to a series circuit of the NMOS transistors 321 and 322,correction data terminal ODD0, and the memory cell 311; a series circuitof NMOS transistors 323 and 324, correction data terminal ODD1, and thememory cell 312; a series circuit of NMOS transistors 325 and 326,correction data terminal ODD2, and the memory cell 313; and a seriescircuit of NMOS transistors 327 and 328, correction data terminal ODD3,and the memory cell 314.

The gates of NMOS transistors 331, 333, 335, and 337 are connected tothe memory cell selecting terminals W0-W3 and the gates of NMOStransistors 332, 334, 336, and 338 are connected to the enable signalterminal E1. The output of the inverter 302 is connected to a seriescircuit of the NMOS transistors 332 and 331 and the memory cell 311, aseries circuit of the NMOS transistors 334 and 333 and the memory cell312, a series circuit of the NMOS transistors 336 and 335 and the memorycell 313, and a series circuit of the NMOS transistors 338 and 337 andthe memory cell 314.

The memory cell group 300-2 is of the same configuration as the memorycell group 300-1 except that the memory cell group 300-2 is connected tothe write-enable signal terminal E2 and correction data terminalsEVN0-EVN3.

{Multiplexer}

FIG. 9 illustrates the configuration of the multiplexer 161 shown inFIG. 7.

Referring to FIG. 9, the correction data terminals ODD0-ODD3 of, forexample, the sub multiplexer 161A1 receive the correction data from thecorrection data terminals ODD0-ODD3 of the sub memory circuit 151A1. Thecorrection data terminals EVN0-EVN3 of the sub multiplexer 161A1 receivethe correction data from the correction data terminals EVN0-EVN3 of thesub memory circuit 151A1. The selection signal terminals S1N and S2N ofthe multiplexer 161A1 receive selection signals from the selectionsignal terminals S1N and S2N of the signal selector 142. Correction dataterminals Q0-Q3 output correction data. P channel MOS transistors(referred to as PMOS transistor hereinafter) 341-348 select input data.

PMOS transistors 341, 343, 345, and 347 are controlled to turn on or offby the selection signal S1N, thereby connecting the correction dataterminals ODD0-ODD3 to the correction data terminals Q0-Q3 ordisconnecting the correction data terminals ODD0-ODD3 from thecorrection data terminals Q0-Q3. The PMOS transistors 342, 344, 346, and348 are controlled to turn on or off by the selection signal S2N appliedto their gates, thereby connecting the correction data terminalsEVN0-EVN3 to the correction data terminals Q0-Q3 or disconnecting thecorrection data terminals EVN0-EVN3 from the correction data terminalsQ0-Q3.

The multiplexer 161A of the above-described configuration employs thePMOS transistors 341-348 as switch elements. The use of the PMOStransistors 341-348 enables a reduction of the number of parts whileensuring reliable operation of the multiplexer 161A.

When the selection signal S1N is set to low (“Low” level) to turn on thePMOS transistor 341, if the correction data ODD0 is at the High level,the correction data Q0 has a substantially equal voltage to the Highlevel of the correction data ODD0. In other words, the PMOS transistor341 can be used to transfer a signal of the High level without anyproblem.

However, if the correction data ODD0 is at the Low level, the potentialof the drain of the PMOS transistor 341 decreases close to the thresholdvoltage of the PMOS transistor 341 but not low enough to become the Lowlevel (nearly 0 volts). Thus, the PMOS transistor 341 presents a problemin transferring a signal of the Low level.

In order to solve the above described drawbacks, a conventional artswitching means employs, for example, an analog switch which is aparallel connection of a PMOS transistor and an NMOS transistor. Thisconfiguration permits generating an output voltage substantially equalto an input voltage and the insertion of a switch means does not causeany difference between the input voltage and output voltage. However,this configuration necessitates the parallel connection of the PMOStransistor and NMOS transistor for each data line, requiring twice asmany components as the configuration shown in FIG. 9. This requires alarger chip area of the IC to accommodate the components.

The configuration of the invention shown in FIG. 9 requires one half asmany components as the conventional art that employs analog switches,but presents a problem in transferring a signal of the Low level.However, it is to be noted that a signal of the High level input intothe driver 181 connected to the outputs of the multiplexer 161 isrequired to be substantially equal to the power supply voltage VDD and asignal of the Low level needs only to be as low as the control voltageVcont which will be described later. In other words, the Low level inputto the driver 181 does not need to be substantially 0 volts. For thisreasons, the multiplexer shown in FIG. 9 is effective in reducing thenumber of components while eliminating constraints in the circuitoperation.

{Driver}

FIG. 10 is a schematic diagram of the driver 181 shown in FIG. 7.

Referring to FIG. 10, a print data terminal E of the driver 181 (e.g.,181-93) receives print data (negative logic) from an inverted outputterminal QN of the latch 131A1. A control terminal S receives a negativelogic drive signal for driving a light emitting thyristor from the NANDgate 146. The correction data terminals Q0-Q3 receive the correctiondata from the correction data terminals Q0-Q3 of the multiplexer 161A1.A control voltage receiving terminal V receives a control voltage Vcontfrom the control voltage output terminal V of the control voltagegenerator 170. The VDD terminal receives the supply voltage VDD. A drivecurrent output terminal DO (i.e., DO93) outputs the drive current to theanode of a corresponding light emitting thyristor via a thin film wiring(not shown).

The print data terminal E and control terminal S are connected to theinput terminals of a 2-input NOR gate 350. The NOR gate 350 has a supplyterminal connected to the supply terminal VDD and a ground terminal towhich the control voltage Vcont is applied. The output terminal of theNOR gate 350 and the correction data terminals Q0-Q3 are connected tothe input terminals of 2-input NAND gates 351-354, respectively. The2-input NAND gates 351-354 have their supply terminals connected to theVDD terminal and ground terminals connected to the control voltagereceiving terminal V to which the control voltage Vcont is applied. Theoutput terminals of the NOR gate 350 is connected to the gates of PMOStransistors 355 a and NMOS 355 b that constitute a complementarysymmetry MOS inverter (CMOS inverter). The PMOS transistor 355 a andNMOS transistor 355 b are connected in series between the VDD terminaland the control voltage receiving terminal V.

The output terminals of the NAND gates 351-354 are connected to thegates of the PMOS transistors 356-359. The gate of the PMOS transistor360 is connected to the output terminal of the CMOS inverter 355. Thesources and drains of the PMOS transistors 356-360 are connected inparallel between the VDD terminal and drive current output terminal DO.The PMOS transistor 360 is a main drive transistor that supplies a largeportion of the light emitting thyristor drive current and the PMOStransistors 356-359 are auxiliary transistors that adjust a smallportion of the light emitting thyristor drive current for each dot,thereby correcting the light output of the light emitting thyristor.

The difference between the voltage (potential) at the VDD terminal andthe control voltage Vcont at the control voltage receiving terminal V issubstantially equal to the gate-source voltage when the PMOS transistors356-360 are turned on. Varying the gate-to-source voltage allowsadjustment of the drain current of the PMOS transistors 356-360. Thecontrol voltage generator 170 shown in FIG. 7, which supplies thecontrol voltage Vcont, controls the control voltage Vcont based on thereference voltage VREF so that the drain currents through the PMOStransistors 356-360 have their corrected values.

The driver 181-93 of the aforementioned configuration operates asfollows.

When the print data received at the print data terminal E is ON (Lowlevel or “L”) and the control signal received at the control terminal Sis ON (Low level or “L”), the output of the NOR gate 350 is at the Highlevel. At this moment, the outputs of the NAND gates 351-354 and theoutput of the CMOS inverter 355 becomes equal to the supply voltage VDDor Vcont in response to the data at the correction data terminals Q3-Q0.

The PMOS transistor 360 is controlled by the print data inputted to theprint data terminal E. The correction data is outputted from the submemory circuit 151A1 (FIG. 8) to the correction data terminals Q0-Q3 ofthe multiplexer 161A1. When the output of the NOR gate 350 goes high,the PMOS transistors 356-359 are selectively driven in accordance withthe correction data that appears at the correction data terminals Q0-Q3.

In other words, when the PMOS transistor 360 is driven, the PMOStransistors 356-359 are also selectively driven, so that the lightemitting thyristor drive current is the sum of the drain current flowingthrough the PMOS transistor 360 and the drain currents flowing throughthe PMOS transistors 356-359, and is supplied to the corresponding lightemitting thyristor from the drive current output terminal DO.

When the PMOS transistors 356-359 are driven, the outputs of the NANDgates 351-354 are low (Low level) (=approximately Vcont), so that thegate voltage of the PMOS transistors 356-359 are nearly equal to thecontrol voltage Vcont. At this moment, the PMOS transistor 355 a is OFFand the NMOS 355 b is ON so that the gate voltage of the PMOS transistor360 is also nearly equal to the control voltage Vcont. This implies thatthe drain currents flowing through the PMOS transistors 356-360 can bedriven by the single control voltage Vcont. At this moment, the NANDgates 351-354 receive the supply voltage VDD at its supply terminal andthe control voltage Vcont at its ground terminal. The input signal canhave a voltage between the supply voltage VDD and the control voltageVcont, and therefore the LOW level need not be 0 volts.

{Memory Controller}

FIG. 11 is a schematic diagram illustrating the configuration of thememory controller 141 shown in FIG. 7.

The latch signal terminal LOAD receives the positive logic latch signalLOAD-P. The drive terminal STB receives a positive logic print drivesignal STB-P outputted from the inverter 144 shown in FIG. 7. The memorycell selecting terminals W0-W3 output the memory selecting signal to thememory circuit 150 shown in FIG. 7. The write-enable signal terminals E1and E2 output the write enable signals to the memory circuit 150. Thememory controller 141 also includes flip flops FFs 361-365, 2-input NORgate 366, 2-input AND gates 367 and 368, and 3-input AND gates 370-373.

The flip-flops FFs 361 and 362 include a negative logic reset terminalR, a clock signal terminal CK, a data input terminal D, and anon-inverted output terminal Q. The reset terminal R receives the latchsignal LOAD-P from the latch signal terminal LOAD. The CLK terminalreceives the positive logic signal print drive signal STB-P from thedrive terminal STB. The output terminal Q outputs the data. Each of theflip-flops FFs 363-365 has a negative logic reset terminal R forreceiving the latch signal LOAD-P from the latch signal terminal LOAD.Each of the flip-flops FFs 363-365 also has a clock terminal CK, a datainput terminal D, a non-inverted output terminal Q, and an invertedoutput terminal QN.

The non-inverted output terminals Q of the flip flops FFs 361 and 362are connected to the inputs of the NOR gate 366. The output of the NORgate 366 is connected to the input terminal D of the flip flop FF 361.The non-inverted output terminal Q of the flip flop FF 361 is fed to theclock terminal CK of the flip flop FF 363 whose output QN is connectedto the input terminal D of the flip flop FF 363. The output terminal Qof the flip flop FF 363 and the latch signal terminal LOAD are connectedto the inputs of the AND gate 367 whose output is connected to the writeenable signal terminal E1. The output QN of the flip flop FF 363 and thelatch signal terminal LOAD are connected to the inputs of the AND gate368 whose output is connected to the write-enable signal terminal E2.

The output of the AND gate 367 is connected to the clock terminals CK ofthe flip flops FFs 364 and 365. The negative logic reset terminals R ofthe flip flops FFs 364 and 365 are connected to the latch signalterminal LOAD. The inverted output terminal QN of the flip flop FF 364is connected to the input terminal D of the flip flop FF 365. Thenon-inverted output terminals Q and inverted output terminal QN of theflip flops FFs 364 and 365 and the non-inverted output terminal Q of theflip flop FF 362 are connected to the input terminals of the AND gates370-373. The outputs of the AND gates 370-373 are connected to thememory cell selecting terminals W0-W3, respectively.

The first input terminal and the second input terminal of the AND gate373 are connected to the non-inverted output terminal Q of the flip flopFF 365 and the inverted output terminal QN of the flip flop FF 364,respectively. The first input terminal and second input terminal of theAND 372 are connected to the non-inverted output terminal Q of the flipflop FF 364 and the output terminal Q of the flip flop FF 365,respectively. The first input terminal and the second input terminal ofthe AND gate 371 are connected to the inverted output terminal QN of theflip flop FF 365 and the non-inverted output terminal Q of the flip flopFF 364, respectively. The first input terminal and the second inputterminal of the AND gate 370 are connected to the inverted outputterminal QN of the flip flop FF 365 and the inverted output terminal QNof the flip flop FF 364, respectively.

{Signal Selector}

FIG. 12 a schematic diagram illustrating the configuration of the signalselector 142 shown in FIG. 7.

The signal selector 142 has a flip flop FF 381 and buffers 382 and 383.The reset terminal R (negative logic) of the flip flop FF 381 receivesthe main scanning sync signal HSYNC-N from the sync signal terminalHSYNC of the driver IC 100. A clock terminal CK receives the latchsignal LOAD-P (positive logic) from the latch signal terminal LOAD. Aninput terminal D is connected to an inverted-output terminal QN. Anon-inverted output terminal Q outputs a non-inverted output. Thesignals appearing on the output terminals Q and QN are fed to theselection signal terminals S2N and S1N through the buffers 382 and 383,respectively.

The signal selector 142 is configured to output the selection signals ofeither the “H” level or the “L” level to the selection signal terminalsS1N and S2N in synchronism with the latch signals LOAD-P received at thelatch signal terminal LOAD.

{Control Voltage Generator}

FIG. 13 illustrates the configuration of the control voltage generator170 shown in FIG. 7.

Each driver IC 100 includes the corresponding control voltage generator170. The control voltage generator 170 includes an operational amplifier391, a PMOS transistor 392, a voltage divider 393 includingseries-connected resistors R00-R15, and an analog multiplexer 394.

The operational amplifier 391 has an inverted input terminal connectedto the VREF terminal, a non-inverted input terminal connected to theoutput terminal Y of the multiplexer 394, and an output terminalconnected to the control voltage output terminal V and the gate of thePMOS transistor 392. The PMOS transistor 392 has the same gate length asthe PMOS transistors 356-360 shown in FIG. 10. The PMOS transistor 392has a source connected to the VDD terminal, a gate connected to theoutput terminal of the operational amplifier 391 and the control voltageoutput terminal V, and a drain connected to the ground terminal GNDthrough the voltage divider 393.

The multiplexer 394 includes 16 input terminals P0-P15 that receiveanalog voltages from junction points of the voltage dividing resistorsR15-R00 connected in series, and input terminals S0-S3 that receivelogic signals from the output terminals Q0-Q3 of the sub memory circuit152 shown in FIG. 7. The four logic signals are used to produce 16different logic combinations for selecting one of the input terminalsP0-P15, thereby outputting a corresponding analog voltage from theoutput terminal Y to the non-inverted input terminal of the operationalamplifier 391. In other words, one of the input terminals P0-P15 isselected in accordance with the logic levels at the input terminalsS3-S0 of the multiplexer 394, thereby establishing a current pathbetween the output terminal Y and the selected one of the inputterminals P0-P15.

The OP amp 391, voltage divider resistors R00-R15, and PMOS transistor392 constitute a feedback control circuit which maintains the voltage atthe non-inverted input terminal of the OP amp 391 substantially equal tothe reference voltage VREF. For this reason, the drain current Iref ofthe PMOS transistor 392 is determined by the resultant resistance ofthose voltage divider resistors R00-R15 selected by the multiplexer 394and the reference voltage VREF inputted to the OP amp 391.

For example, when the input terminals S3-S0 of the multiplexer 394 areat logic levels “1,” “1,” “1,” and “1” (i.e., maximum value),respectively, the input terminal P15 is connected to the output terminalY so that the voltage at the input terminal P15 is substantially thesame as the reference VREF. Consequently, the drain current Iref of thePMOS transistor 392 is given as follows:

Iref=VREF/R00

On the other hand, the logic levels at the terminals S3-S0 are “0,” “1,”“1,” and “1” (i.e., medium value), the input terminal P7 is connected tothe output terminal Y so that the voltage at the input terminal P7 issubstantially the same as the reference voltage VREF. Consequently, thedrain current Iref of the PMOS transistor 392 is given as follows:

Iref=VREF/(R00+R01+R02+R03+R04+R05+R06+R07+R08)

When the logic levels at the terminals S3-S0 are “0000” (i.e., minimumvalue), the input terminal P0 of the multiplexer 394 is connected to theoutput terminal Y of the multiplexer 394 so that the drain current Irefof the PMOS transistor 402 is given as follows:

Iref=VREF/(R00+R01+R02 . . . . . . +R15)

The PMOS transistors 356-360 shown in FIG. 10 and the PMOS transistor392 shown in FIG. 13 have the same gate length and are driven to operatein their saturation regions, and so one of the PMOS transistorsconstitutes a current mirror of the other. When the PMOS transistors356-360 become ON, the drain current Iref is proportional to thereference voltage VREF. Therefore, the drain current Iref can beadjusted in 16 increments by selectively setting the logic levels at theinput terminals S3-S0 of the multiplexer 394. Thus, the drain currentsthrough the PMOS transistors 356-360 can also be adjusted in 16increments.

{Gate Driver}

FIGS. 14A and 14B illustrate the configuration of the first and secondgate drivers 162 and 163 shown in FIG. 7. FIG. 14A illustrates thecircuit symbol of the gate drivers 162 and 163. FIG. 14B is a circuitschematic of the gate drivers 162 and 163.

The first gate driver 162 and second gate driver 163 are substantiallyidentical in configuration. The first gate driver 162 has an inputterminal IN connected to the selection signal terminal S1N of the signalselector 142. An inverter 401 has an input terminal connected to theinput terminal IN and an output node N401 connected to the inputterminal of an inverter 402 and the input terminal of a timing adjustingcircuit 405. The timing adjusting circuit 405 takes the form of ananalog switch implemented with a parallel connection of an NMOStransistor 405 a and a PMOS transistor 405 b. The output node N405 ofthe timing adjusting circuit 405 is connected to the gate of a firstswitch element, e.g., PMOS transistor 403. The gate of the NMOStransistor 405 a is connected to the VDD terminal and the gate of thePMOS transistor 405 b is connected to the ground GND.

The source of the PMOS transistor 403 is connected to the VDD terminal.The drain of the PMOS transistor 403 is connected to the source of avoltage level shifter or a PMOS transistor 406. The gate and drain ofthe PMOS transistor 406 are connected to the output terminal OUT. Theoutput terminal OUT is connected to the ground GND through thesource-drain of a second switch element, e.g. PMOS transistor 404. Thegate of the PMOS transistor 404 is connected to an output node N402 ofthe inverter 402.

FIG. 15 illustrates a gate driver 162A as a comparative example.

The gate driver 162A does not include the timing adjusting circuit 405and the PMOS transistor 406 (FIG. 14B). The output terminal of theinverter 401 is connected to the gate of the PMOS transistor 403. Thedrain of the PMOS transistor 403 is connected to the output terminalOUT.

When the input terminal IN of the gate driver 162A goes high (“High”level), the output terminal of the inverter 401 goes low (“Low” level),and the output terminal of the inverter 402 goes high (“High” level).Thus, the PMOS transistor 403 becomes ON and the PMOS transistor 404becomes OFF, causing the output terminal OUT to rise to a voltagesubstantially equal to the power supply voltage VDD.

In contrast, the gate driver 162 of the present invention (FIG. 14B)employs the timing adjusting circuit 405.

The timing adjusting circuit 405 serves to delay the signal by asubstantially equal amount of time to the delay time of the inverter402, so that the PMOS transistor 403 turns on substantially at the sametime that the PMOS transistor 404 turns off, and so that the PMOStransistor 403 turns off substantially at the same time that the PMOStransistor 404 turns on. This prevents malfunction of the circuit due toa crowbar current that would otherwise flow from the VDD terminal to theground GND through the PMOS transistors 403, 406, and 404.

In other words, if the timing adjusting circuit 405 is not employed,both the PMOS transistor 403 and PMOS transistor 404 may be turned onsubstantially simultaneously for a short period of time equal to thedelay time of the inverter 402. This causes a crowbar current betweenthe VDD terminal and the ground GND, resulting in a high noise voltagein VDD terminal or the ground wirings and hence malfunction of theinternal circuit of the driver IC 100. The gate drivers 162 and 163 ofthe present invention employ the timing adjusting circuits 405 toprevent the driver IC 100 from malfunctioning.

The timing adjusting circuit 405 of the first embodiment takes the formof an analog switch but may be another form of switch. For example, thetiming adjusting circuit 405 may be constituted of an even number ofinverters. If crowbar current is not critical to the circuit operation,the output node N401 of the inverter 401 may be directly connected tothe gate of the PMOS transistor 403 instead of employing the timingadjusting circuit 405.

{Overall Operation of Optical Print Head}

FIG. 16 is a timing chart illustrating the transferring of thecorrection data performed in the optical print head 13 after power-up ofthe image forming apparatus 1 of the first embodiment.

Prior to the transferring of the correction data, the latch signalHD-LOAD is set to the High level indicating that the correction datawill follow (portion I).

The correction data for one dot is 4-bit data. The data for bit 3, byway of example, of the correction data for an odd-numbered dot isinputted from the print data signals HD-DATA3 to HD-DATA0 into the shiftregister 110 constituted of the flip flops FF 111A1 to FF 111D24 (FIG.7), while being shifted by one position upon each clock signal HD-CLK.Upon completion of shifting, three consecutive pulses of the print drivesignal HD-STB-N are inputted as depicted at portion A, enabling thememory controller 141 shown in FIG. 11 to operate.

The signals Q1, Q2, Q3, Q4, and Q5 shown in FIG. 16 are signals thatappear on the output terminals of the flip flops FFs 361, 362, 363, 365,and 364 shown in FIG. 11, respectively. The write-enable signalterminals E1 and E2 are connected to the outputs of the AND gates 367and 368. The memory cell selecting terminals W3-W0 are connected to theoutputs of the AND gates 373, 372, 371, and 370. The selection signalterminals S1N and S2N are connected to the output terminals of thebuffers 383 and 382 shown in FIG. 12, respectively.

When the first pulse of the print drive signal HD-STB-N is received asdepicted at portion “A,” the signal Q1 appears (portion J). When thesecond pulse of the print drive signal HD-STB-N is received, the signalQ2 appears (portion K). The signal Q3 appearing on the output terminalof the flip flop FF 363 turns each time the signal Q1 appears. Forexample, the signal Q3 goes high at the first signal at the outputterminal Q1 as illustrated in FIG. 16, and goes low at the second signalat the output terminal Q1. The signals at the output terminals QN and Q3of the flip flop FF 363 are fed to the AND gates 367 and 368,respectively, the AND gates 367 and 368 outputting the write-enablesignals E1 and E2.

The signal at the Q4 terminal rises as depicted at portion M on therising edge of the write-enable signal E1. The signal at the Q5 terminalrises on the next rising edge of the write-enable signal E1. The signalat the Q4 terminal falls on the still next rising edge of thewrite-enable signal E1. The signal at the Q5 terminal falls on thefurther next rising edge of the write-enable signal E1.

The memory cell selecting signals W3-W0 are generated in order, eachhaving two consecutive pulses (e.g., portions O and P) are generated onthe rising edge of the signal on the Q2 terminal.

Data is written into the memory circuit 151 shown in FIG. 8 on the twopulses of the writes signals W3-W0, the data for odd-numbered dots beingwritten on the first pulse into the memory cells 311-314 in the memorycell group 300-1 and the data for even-numbered dots being written onthe second pulse into the memory cells in the memory cell group 300-2.

The first pulses (e.g., portion Q) of the memory selecting signals W3-W0are clocked by the print drive signal HD-STB-N at portions A, C, E, andG and the second pulses (e.g., portion P) of the memory selectingsignals W3-W0 are clocked by the print drive signals HD-STB-N atportions B, D, F, and H.

Once all of the correction data for bit3-bit0 (ODD3-ODD0 and EVN3-EVN0)have been written into the memory cell groups 300-1 and 300-2, the latchsignal HD-LOAD is set to the Low level as depicted at portion Q,allowing the print data signals HD-DATA3 to HD-DATA0 to be transferredto the multiplexer 161. The main scanning sync signal HD-HSYNC-N asdepicted at portion R is input into the driver IC 100, indicating thatthe data for the odd numbered dots will be transferred prior to printingof one line.

The print data signals HD-DATA3 to HD-DATA0 for the odd-numbered dotsare shifted through the shift register 110, i.e., through the flip-flopsFF 111A1 to FF 111D1, . . . FF 111A24 to FF 111D24 as depicted atportion U, and are then latched into the latch circuit 130 on the latchsignal HD-LOAD at portion S.

The print drive signal HD-STB-N then goes low (Low level) as depicted atportion W, thereby causing the light emitting thyristors 211-1, 211-2, .. . 211-96 and 212-1, 212-2, . . . 212-96 (FIG. 5) to emit light. Thelight emitting thyristors 211-1, 211-2, . . . 211-96 and 212-1, 212-2, .. . 212-96 continue to emit light as long as the print drive signalHD-STB-N remains at a low level as depicted at portion W and portion X.

Likewise, the print data signals HD-DATA3 to HD-DATA0 for the evennumbered dots are shifted through the shift register 110 at portion V.

As shown in FIG. 7, the selection signal S1N outputted from the signalselector 142 is fed to the first gate driver 162 (FIG. 14B), which inturn outputs the gate drive signal G1 to the odd-numbered light emittingthyristors 212 through the common wiring 220 a. The selection signalsS2N outputted from the signal selector 142 is fed to the second gatedriver 163 (FIG. 14B), which in turn outputs the gate drive signal G2 tothe even-numbered light emitting thyristors 211 through a common wiring220 b.

{Details of Transfer of Correction Data}

FIGS. 17-20 are timing charts illustrating waveforms of the respectivesignals using one of the driver ICs 100-1, 100-2, . . . , 100-26.

FIG. 17 illustrates the details of portions A and B shown in FIG. 16.FIG. 18 illustrates the details of portions C and D shown in FIG. 16.FIG. 19 illustrates the details of portions E and F shown in FIG. 16.FIG. 20 illustrates the details of portions G and H.

Referring to FIG. 16, the chip correction data chip-b3, chip-b2,chip-b1, and chip-b0 to be set for each driver IC 100 need to betransferred only for either odd-numbered dots (e.g., portion “A”) oreven-numbered dots (e.g., portion “B”).

For this purpose, the shift register 110 shown in FIGS. 17-20 has onemore stage when the correction data for the odd-numbered dots (portionsA, C, E, G, etc.) is shifted than when the correction data for theeven-numbered dots is shifted. The chip correction data is added to thetop of the string of data when the data is outputted from the printingcontroller 40.

{Operation of Gate Drivers}

FIGS. 21A and 21B illustrate the first and second gate drivers 162 and163 shown in FIG. 7 for driving the gates of the light emittingthyristor 210. FIG. 21A illustrates the symbol of the light emittingthyristor 210 and the voltage and current at the respective terminals.FIG. 21B is an equivalent circuit of the light emitting thyristor 210connected to the first gate driver 162, the light emitting thyristor 210being constituted of the PNP transistor 221 and the NPN transistor 222.

The operation of the light emitting thyristor 210 will be described.Assume that the input of the gate driver 162 (or 163) is at the Lowlevel. The output node N401 of the inverter 401 in the gate driver 162is at the High level. Since the timing adjusting circuit 405 is in theON state at all times, the output node N405 of the timing adjustingcircuit 405 is also at the High level so that the PMOS 403 is OFF.

The output node N402 of the inverter 402 of the first gate driver 162 isat the Low level, so that the PMOS transistor 404 in ON to bring thevoltage at the output terminal OUT to the Low level. The voltage at theoutput terminal OUT is equal to the gate-source voltage Vgs of the PMOStransistor 404, and will decrease to a final value, i.e., the thresholdvoltage Vt of the PMOS transistor 404.

In order to drive the light emitting thyristor 210, the drive currentoutput terminal DO of the driver IC 100 shown in FIG. 5 outputs an anodecurrent Ia. The anode current Ia is a forward current that flows througha PN junction (i.e., base-to-emitter of the PNP transistor 221) to causea gate current Ig. This causes an anode voltage Va to appear across theanode and cathode of the light emitting thyristor 210. The gate voltageat this moment is Vgs.

The gate current Ig is a part of the base current Ib of the PNPtransistor 221, resulting in the collector current through the PNPtransistor 221. The collector current flows as the base current into theNPN transistor 222 causing the NPN transistor 222 to conduct. Thecollector current of the PNP transistor 221 causes the base current ofthe PNP transistor 221 to further increase, accelerating the transitionof the PNP transistor from the OFF state to the ON state.

After the NPN transistor 222 has turned on completely, thecollector-emitter voltage of the NPN transistor 222 is lower than thethreshold Vt of the PMOS 404 of the first gate driver 162 shown in FIG.14B. As a result, the gate current Ig, which would otherwise flow fromthe gate of the light emitting thyristor 210 shown in FIGS. 21A and 21Bto the output terminal OUT, is nearly zero, and a cathode current Iksubstantially equal to the anode current Ia flows so that the lightthyristor 210 becomes ON completely.

FIGS. 21C, 21D, and 21E illustrate changes in the anode voltage Va, gatecurrent Ig, and gate-cathode Voltage Vgk with the anode current Ia,respectively, when the light emitting thyristor 210 shown in FIGS. 21Aand 21B turns on.

FIG. 21C plots the anode current Ia as the abscissa and the anodevoltage Va as the ordinate.

When the light emitting thyristor 210 is OFF, the anode current Ia issubstantially zero, which is shown at the origin (0, 0) of the FIG. 21C.When the anode voltage Va begins to increase as shown in FIG. 21C toreach a voltage Vp, the anode-gate voltage Vag of the light emittingthyristor 210 is equal to the emitter-base voltage Vbe of the PNPtransistor 221, and the output voltage VoL of the first gate driver 162at the Low level is equal to the gate-source voltage Vgs of the PMOS 404of the first gate driver 162 shown in FIG. 14B. Thus, there is thefollowing relationship among Vp, Vag, VoL and Vgs.

Vp=Vag+VoL=Vag+Vgs

The voltage Vp is a forward voltage that causes a maximum value of thegate current Ig (i.e., the base current Ib of the PNP transistor 221) toflow. A circled portion (Ip, Vp) on the curve shown in FIG. 21Cindicates a boundary between the OFF region Z1 of the light emittingthyristor 210 and the ON region Z2.

As the anode current Ia increases, the anode voltage Va increases,eventually reaching a point (Iv, Vv) shown in FIG. 21C, which is aboundary between the ON region Z2 and the ON region Z3 of the lightemitting thyristor 210. When the anode current Ia has reached Iv, thegate current Ig has decreased to substantially zero. This implies thatthe first gate driver 162 is effectively disconnected from the gate ofthe light emitting thyristor 210.

As the anode current Ia further increases, the anode voltage Va furtherincreases, finally reaching a point (I1, V1) shown in FIG. 21C where thelight emitting thyristor 210 emits light produced by the an anodecurrent I1 supplied from the driver IC 100.

FIG. 21D illustrates changes in the gate current drawn to the same scaleof the anode current as in FIGS. 21C. FIG. 21D illustrates therelationship among the gate current Ig, the peak value of Ig1 of thegate current Ig, the anode voltage Vp, and the anode current Ip.

FIG. 21E illustrate changes in the gate-cathode voltage Vgk with theanode current of the light emitting thyristor, and plots the anodecurrent Ia as the abscissa and the gate-cathode voltage Vgk as theordinate.

When the light emitting thyristor begins to turn on, the gate current Igis developed to determine the output voltage VoL, which is equal to thegate-cathode voltage Vgk of the light emitting thyristor 210. When thelight emitting thyristor 210 becomes completely turned ON, i.e., whenthe NPN transistor 222 is in its saturation region, the output voltageVoL decreases to a voltage V2 shown in FIG. 21E. The voltage V2corresponds to the emitter-collector saturation voltage Vce (sat) of theNPN transistor 222.

Thus, the gate-source voltage of the PMOS transistor 404 in the firstgate driver 162 is lower than the threshold Vt i.e., V2<Vt, so that thePMOS transistor 404 is in its OFF region or a sub threshold region to beexact, and the gate current Ig shown in FIG. 21B falls to substantiallyzero.

As described above, the first gate driver 162 shown in FIG. 14B is usedto prevent the gate current Ig from flowing out of the light emittingthyristor 210 after the light emitting thyristor 210 has turned on,thereby holding the light emitting thyristor 210 in its ON state withthe anode current Ia substantially equal to the cathode current Ik. Thisimplies that adjusting the anode current Ia provides a correspondinglight output. This operation is achieved by employing the PMOStransistor 404 at the output of the first gate driver 162 shown in FIG.14B.

In contrast, if an NMOS transistor is used in place of the PMOS 404 justas in the conventional CMOS output circuit, the low level output VoL ofthe first gate driver 162 would decrease to substantially 0 volts,allowing the base current Ib of the PNP transistor 222 to continue toflow as the gate current Ig into the first gate driver 162. Thus, thecollector current of the PNP transistor 222 decreases by the gatecurrent Ig accordingly, causing the cathode current Ik of the lightemitting thyristor 210 to decrease. Thus, the light output of the lightemitting thyristor 210 may fluctuate. The first gate driver 162 (FIG.14B) according to the first embodiment effectively prevents such adrawback.

Next, the operation of the first gate driver 162 shown in FIGS. 14A and14B when outputting the high level output signal will be described. Thisoperation corresponds to when the light emitting thyristor 210 shown inFIG. 21A is in its OFF state.

For example, assume that the input terminal IN of the first gate driver162 is at the High level. At this moment, the output node N401 of theinverter 401 in the first gate driver 162 is at the Low level, and theoutput node N402 of the inverter 402 is at the High level so that thePMOS transistor 404 is in its OFF state.

Since the timing adjusting circuit 405 is in its ON state at all times,when the node N401 goes low (Low level), the output node N405 of thetiming adjusting circuit 405 is also in its Low level, causing the PMOStransistor 403 to turn on. Thus, the drain voltage of the PMOS 403 issubstantially equal to the supply voltage VDD, causing the PMOStransistor 406 connected to the PMOS transistor 403 to turn on so thatthe output terminal OUT goes high (High level).

Because the gate of the PMOS transistor 406 is connected to the outputterminal OUT, when the output terminal OUT reaches the potential equalto VDD-Vt, the gate-source voltage Vgs of the PMOS transistor 406 willhave reached a value substantially equal to the threshold voltage Vt sothat the PMOS transistor 406 turns off. In this manner, even though theoutput terminal OUT of the first gate driver 162 goes high (High level),the potential of the output terminal OUT increases only to a potentialequal to VDD-Vt and will not further increase to the supply voltage VDDas opposed to a comparative gate driver 162A shown in FIG. 15 in whichthe output terminal OUT will go up to the supply voltage VDD.

{Changes in Drive Signals}

FIG. 22A is a simple model representation illustrating only two lightemitting thyristors, i.e., 211-1 and 212-1 shown in FIG. 5.

The driver IC 100 includes a driver 181 having a drive current outputterminal DO, the first gate driver 162 that receive selecting signal S1Nand outputs gate drive signal G1, and the second gate driver 163 thatreceive selecting signal S2N and outputs gate drive signal G2. Theanodes of the light emitting thyristors 211-1 and 212-1 are connected tothe drive current output terminals DO of the driver IC 100. The gate ofthe light emitting thyristor 212-1 is connected to the gate drive signalterminal G1 of the driver IC 100 and the gate of the light emittingthyristors 211-1 is connected to the gate drive signal terminal G2 ofthe driver IC 100.

Thus, in the optical print head, the gate drive signal terminal G1 isconnected to the gates of a plurality of light emitting thyristors212-1, 212-2, 212-3, . . . via the common wires 220 a. The gate drivesignal terminal G2 is connected to the gates of a plurality of lightemitting thyristors 211-1, 211-2, 211-3, . . . via the common wires 220b. FIG. 22A illustrates only one light emitting thyristor 211-1 and onlylight emitting thyristor 212-1.

The drive current output terminals DO supply the drive current or anodecurrent Ia to the light emitting thyristors 211-1 and 212-1. The firstand second gate drivers 162 and 163 supply the gate currents Ig1 and Ig2to the light emitting thyristors 212-1 and 211-1. The gate-cathodevoltage Vgk1 is the gate-cathode voltage of the light emittingthyristors 212-1 and the gate-cathode voltage Vgk2 is the gate-cathodevoltage of the light emitting thyristor 211-1.

FIG. 22B is a timing chart illustrating the operation of the lightemitting thyristors 211-1 and 212-1 shown in FIG. 22A.

The light emitting thyristor 211-1 and 212-1 are driven in a timedivision manner. The latch signal terminal LOAD corresponds to the latchsignal HD-LOAD shown in FIG. 5. The print drive signal STB-N is anegative logic strobe signal inputted to the STB terminal shown in FIG.7 and corresponds to the print drive signal HD-STB-N shown in FIG. 5.

The signal selector 142 shown in FIG. 7 outputs the selection signal S1Nto the first gate driver 162 and the selection signal S2N to the secondgate driver 163. The output of the first gate driver 162 is used as thegate drive signal G1 for the light emitting thyristor 212-1. The outputof the second gate driver 163 is used as the gate drive signal G2 forthe light emitting thyristor 211-1.

The main scanning synch signal HSYNC-N is input to the driver IC 100 toreset the driver IC 100, so that the selection signal S1N is at the Highlevel and the selection signal S2N is at the LOW level. These selectionsignals S1N and S2N are input to the first and second gate drivers 162and 163, respectively. The first gate driver 162 outputs the gate drivesignal G1 of the High level and the second gate driver 163 outputs thegate drive signals G2 of the Low level.

When the gate drive signals G1 and G2 are at the High level, i.e., VoHis equal to VDD-Vgs where VDD is the power supply voltage and Vgs is thegate-source voltage of the PMOS transistor 406. When the gate drivesignals G1 and G2 are at the Low level, VoL is equal to Vgs which is thegate-source voltage of the PMOS transistor 404. The gate-source voltageVgs is slightly higher than a threshold voltage Vt.

The gate-source voltage Vgs may be changed by adjusting the substratebias voltage across the source and the substrate, the gate length of thePMOS transistors 406 and 404, or the gate width of the PMOS transistors406 and 404. For example, if the power supply voltage VDD=5 V and VoL=2V, then the VoH=3 V and VoL=2 V. These values are shown in FIG. 22B.

Referring to FIG. 22B, upon reception of the latch signal LOAD at timeT1 (portion A), the selection signal S1N goes low (Low level) and theselection signal S2N goes high (High level) (portion B). This in turncauses the gate-cathode voltage Vgk1 decreases from about 3V to about 2V(portion C) and the gate-cathode voltage Vgk2 increases from about 2 Vto about 3 V.

The print drive signal STB-N for energizing the light emitting thyristor212-1 goes low (portion E) at time T2, so that the anode current Iarises (portion F). As described in FIG. 21A, apart of the anode currentIa injected into the anode flows out from the gate as the gate currentIg so that the light emitting thyristor 212-1 turns on.

A hatched portion depicted at H of the anode current Ia corresponds tothe gate current Ig1 denoted at G. The gate current Ig1 flows into thefirst gate driver 162, so that the output voltage of the first gatedriver 162 somewhat increases (portion I). Since the light emittingthyristor 212-1 turns on, the output voltage of the first gate driver162 will go down to about 0.2V (portion K). The value of 0.2Vcorresponds to the Vce(sat), which is the collector-emitter saturationvoltage of the NPN transistor 222 described with reference to FIG. 21B.

At this moment, the gate current Ig1 causes the light emitting thyristor212-1 to turn on to emit light. It is to be noted that the gate-cathodevoltage Vgk2 of the light emitting thyristor 211-1 is about 3V which isthe High level, not causing the gate current Ig2 to flow from anode togate. Thus, the light emitting thyristor 211-1 remains turned off.

At time T3, the print drive signal STB-N goes high (High level) atportion L, causing the anode current Ia to decrease as depicted at M.When the anode current Ia decreases below a holding current determinedby the characteristics of the light emitting thyristors 211-1 and 212-1,the light emitting thyristors 211-1 turns off, the anode voltage risingup to cause the gate current Ia at portion N. The gate current Ig1 atportion N is caused by the anode current Ia at a hatched portiondepicted at O. As the gate current Ig1 at portion N diminishes, thelight emitting thyristor 212-1 turns off so that the gate-cathodevoltage Vgk1 increases at portion P to become about 2V which is the Lowlevel (=VoL) of the buffer 162.

At time T4, the latch signal LOAD is input to the driver IC 100, asshown at portion Q, and the selection signal S1N goes high (High level)at portion R, and the selection signal S2N goes low. Then, the gatedrive signals G1 and G2 go high (High level) and low (Low level),respectively. The output voltage VoH of the High level of the buffer 162is about 3 V as depicted at portion S and will not increase to the powersupply voltage VDD. Also, the gate-cathode voltage Vgk2 decreases toabout 2 V as depicted at portion T.

At time T5, the print drive signal STB-N goes low (Low level) asdepicted at portion U to cause the anode current Ia again to rise asdepicted at portion V. As described with reference to FIG. 21B, aportion of the anode current Ia flows out from the gate to become a gatecurrent Ig2 when the light emitting thyristor 211-1 is being turned on.The gate current Ig2 causes the light emitting thyristor 211-1 to turnon.

A hatched portion depicted at X of the anode current Ia corresponds tothe gate current Ig2, denoted at G, of the light emitting thyristor211-1. The gate current Ig2 flows into the second gate driver 163, sothat the output voltage of the second gate driver 163 somewhat increases(portion Y). As the light emitting thyristor 211-1 turns on, the outputvoltage of the second gate driver 163 will decrease to about 0.2V(portion Z). The value of 0.2V corresponds to the Vce(sat), which is thecollector-emitter saturation voltage of the NPN transistor 222 describedwith reference to FIG. 21B.

At this moment, the gate current Ig2 causes the light emitting thyristor211-1 to turn on to emit light. It is to be noted that the gate-cathodevoltage Vgk1 of the light emitting thyristor 212-1 is about 3V which isthe High level, not causing the gate current Ig1 to flow from anode togate. Thus, the light emitting thyristor 212-1 remains turned off. Attime T6, the print drive signal STB-N again goes high (the High level).

In this manner, the gate drive signals G1 and G2 are switched betweenthe High level and the Low level alternately, the gate drive signals G1and G2 being in opposite levels. In other words, when the gate drivesignal G1 is at the Low level and the gate drive signal G2 is at theHigh level, the light emitting thyristor 212-1 turns on and the lightemitting thyristor 211-1 turns off. When the gate drive signal G1 is atthe High level and the gate drive signal G2 is at the Low level, thelight emitting thyristor 212-1 turns off and the light emittingthyristor 211-1 turns on.

Thus, the print drive signal STB-N at portion E shown in FIG. 22B causesthe light emitting thyristor 212-1 to turn on and the light emittingthyristor 211 to turn off. The print drive signal STB-N at portion Ucauses the light emitting thyristor 211-1 to turn on the light emittingthyristor 212 to turn off.

As described above, the light emitting thyristors 211-1 and 212-1 areturned on when the anode currents Ia flow therethrough, and their lightoutputs depend on the value of the anode current Ia. The light emittingthyristors 211-1 and 212-1 can be turned off by setting the anodecurrents Ia to zero. The anode current Ia may be set to zero by settingthe print data signals HD-DATA3 to HD-DATA0 to their off state asdepicted at the portions U and V shown in FIG. 16.

Modification 1 to First Embodiment

FIG. 23 is a schematic diagram illustrating a first gate driver 162Bwhich is a modification to the first gate driver 162 shown in FIG. 14B.Elements common to those shown in FIG. 14B have been given the samereference numerals.

The first gate driver 162B has the same configuration as the first gatedriver 162 except that the PMOS transistor 406 is inserted between theVDD and the PMOS transistor 403. In other words, the PMOS transistor 406has its source connected to the VDD terminal and its gate and drainconnected to the source of the PMOS transistor 403. The drain of thePMOS transistor 403 is connected to the output terminal OUT.

The operation of the first gate driver 162B will be described. Forexample, when the input terminal IN of the first gate driver 162B is atthe Low level (about 0 V), the output node N401 of the inverter 401 isat the High level (about 5 V) and the output node N402 of inverter 402is at the Low level (0 V). At this moment, the PMOS transistor 403becomes off and the PMOS transistor 404 becomes on, so that the outputterminal OUT decreases to the output voltage VoL. The output voltage VoLis substantially equal to the gate-source voltage Vgs of the PMOStransistor 404. The gate-source voltage Vgs depends on thethreshold-voltage Vt of the PMOS transistor 404, and is typically about2V.

When the input terminal IN of the first gate driver 162B is at the Highlevel (about 5 V), the output node N401 of the inverter 401 is at theLow level (about 0 V) and the output node N402 is at the High level(about 5 V). At this moment, the PMOS transistor 404 goes off and thePMOS transistor 403 goes on, causing the gate voltage of the PMOStransistor 406 to decrease so that the PMOS transistor 406 also becomeson and the output terminal OUT goes high (High level) to the outputvoltage VoH. The output voltage VoH is substantially equal to VDD-Vgs,where VDD is about 5 V. The gate-source voltage Vgs depends on thethreshold voltage Vt of PMOS transistors, and is typically about 2 V.Therefore, the output voltage VoH is about 3 V.

Modification 2 to First Embodiment

FIG. 24 is a schematic diagram illustrating a first gate driver 162Cwhich is a modification to the first gate driver 162 shown in FIG. 14B.Elements similar to those in FIG. 14B have been given like referencenumerals.

The gate driver 162C includes a first switch 407 (for example NMOS) thatoperates to set the output voltage VoH below the supply voltage VDD.

The first gate driver 162C also has a second switch (For example PMOS)404. The gates of the NMOS transistor 407 and PMOS transistor 404 areconnected to the input terminal IN. The NMOS transistor 407 has itsdrain connected to the VDD terminal and its source connected to theoutput terminal OUT and the source of the PMOS transistor 404. The drainof the PMOS 404 is connected to the ground GND.

Next, the operation of the gate driver 162C shown in FIG. 24 will bedescribed. For example, when the input terminal IN of the first gatedriver 162 is at the Low level (substantially 0 volts), the PMOStransistor 404 is ON, causing the voltage at the output terminal OUT tothe VoL. The VoL corresponds to the gate-source voltage Vgs of the PMOStransistor 404 and is determined by the threshold voltage Vt. The VoL istypically about 2V.

When the input terminal IN of the first gate driver 162C is at the Highlevel (about 5 V), the NMOS transistor 407 becomes ON, causing thepotential at the output terminal OUT to rise to the high level outputVoH. The VoH corresponds to VDD-Vgs, where VDD (about 5 V) is the supplyvoltage and Vgs is the gate-source voltage of the NMOS transistor 407.The voltage Vgs is determined by the threshold voltage of the NMOStransistor 407 and is typically about 2 V. Therefore, the VoH is about 3V.

The gate driver 162B shown in FIG. 23 and the gate driver 162C shown inFIG. 24 operate in a manner similar to the first gate driver 162 shownin FIG. 14B to set the low level output VoL higher than 0 volts and thehigh level output VoH lower than the supply voltage VDD (5 V). Thus, thegate current Ig can be substantially zero after the light emittingthyristor 210 has turned on and the voltage applied across the gate andcathode can be lower than the breakdown voltage of the light emittingthyristor 210.

Effects of First Embodiment

The gate drivers 162, 162B, 162C, and 163, the driver IC 100incorporating these gate drivers, and optical print head 13 provide thefollowing effects.

When the driver IC 100 drives the gate of the light emitting thyristor210 in a time division manner, the gates of light emitting thyristors tobe energized are set to the Low level and those of light emittingthyristors not to be energized are set to the High level. Generallyspeaking, the driver IC 100 is manufactured using a standard CMOSprocess, and operates at a 5V supply voltage. The comparative gatedriver 162A shown in FIG. 15 has the High level substantially equal toVDD (5 V) and the light emitting thyristor 210 can sustain on about 7 Vwhich is not sufficient. Therefore, in some cases, the light emittingthyristor 210 may be damaged by a signal of the High level.

However, the first gate drivers 162, 162B (modification 1), and 162C(modification 2) can output a high level output signal having a voltagelower than supply voltage VDD (5 V), thereby maintaining thegate-cathode voltage of the non-energized light emitting thyristors to avalue lower than the sustaining voltage of the light emittingthyristors. This prevents the light emitting thyristors from beingdamaged.

The image forming apparatus 1 according to the first embodiment,modification 1, and modification 2 employs the optical print head 13incorporating the driver IC 100. Thus, a high quality image formingapparatus (printer, copying machine, facsimile machine, and MFP) withexcellent space efficiency and light output efficiency can be obtained.In other words, the optical print head 13 can be effectively used inmonochrome image forming apparatus and multi color image formingapparatus as well as in the aforementioned full color image formingapparatus 1. The use of the optical print head 13 is particularlyeffective when employed in a full color image forming apparatus thatemploys a plurality of exposing units.

Second Embodiment {Configuration of Gate Driver}

FIGS. 25A-25C illustrate the configuration of a gate driver according toa second embodiment. FIG. 25A is a schematic diagram illustrating thegate driver. FIG. 25B is a top view illustrating the configuration of anNPN transistor shown in FIG. 25A. FIG. 25C is a cross-sectional view ofthe gate driver taken along a line 25C-25C in FIG. 25B. Elements of thegate driver 162 shown in FIGS. 25A-25C similar to those shown in FIG.14B have been given the same reference numerals.

Referring to FIG. 25A, just as in the first embodiment, a gate driver162D includes a first switch element 408 (e.g., NPN transistor)corresponding to the PMOS transistor 403, and a second switch element404 (e.g., PMOS transistor). The base of the NPN transistor 408 and thegate of the PMOS transistor 404 are connected to an input terminal IN.The NPN transistor 408 has a collector connected to a supply voltageterminal VDD and an emitter connected to an output terminal OUT. ThePMOS transistor 404 has a drain connected to the ground GND and a sourceconnected to the output terminal OUT.

Referring to FIGS. 25B and 25C, the NPN transistor 408 includes an Nwell region 408 b, a P well region 408 c, and an N type region 408 d,all being formed in a silicone-based P type semiconductor substrate 408a. The N well region 408 b is formed in the shape of an island bydiffusing an N type impurity in a predetermined area of a P typesemiconductor substrate 408. The P type well region 408 c is formed inthe shape of an island by diffusing a P type impurity in the N wellregion 408 b. The N type region 408 d is formed in the P well region bydiffusing an N type impurity.

Referring to FIG. 25C, the N well region 408 b, the P well region 408 c,and an N type region 408 d form an N-P-N three-layer structure. Thoughnot specifically shown in FIG. 25C, electrodes are formed on the N wellregion 408 b, P well region 408 c, and N type region 408 d to form anNPN transistor 408. The N well region 408 b serves as a collector, the Pwell region 408 c serves as a base, and the N type region 408 d servesas an emitter.

{Operation of Gate Driver}

When the input terminal IN is at the Low level (about 0 V), the PMOS 404becomes ON causing the voltage at the output terminal OUT to decreasethe Low level (i.e., VoL). The Low level output voltage VoL correspondsto the gate-source voltage Vgs of the PMOS transistor 404, and isdetermined by the threshold voltage Vt of the PMOS transistor 404,typically about 2 V.

When the input terminal IN is at the High level (about 5 V), the NPNtransistor 408 turns on to increase the voltage at the output terminalOUT to the High level output voltage, VoH. The VoH is substantiallyequal to VDD-Vbe, which is typically about 0.6 V. Thus, the VoH is about4.4 V.

As described above, the gate driver 162D operates in the same way as thegate driver 162 of the first embodiment (FIG. 14B). That is, the Lowelevel output voltage VoL is higher than 0 V and the High level outputvoltage VoH is lower than the supply voltage VDD (about 5 V). Thus, thegate current of the light emitting thyristor 210 is substantially zeroafter the light emitting thyristor 210 shown in FIG. 5 has turned on.When the light emitting thyristor 210 is in its OFF state, the voltageapplied across the gate and cathode can be lower than the breakdownvoltage of the light emitting thyristor 210.

{Changes in Drive Signals}

FIG. 26 is a timing chart illustrating the operation of two adjacentlight emitting thyristors 211-1 and 212-1 shown in FIG. 22A when the twogate drivers 162D are used.

Just as in FIG. 22B (first embodiment), the thyristors 211-1 and 212-1are driven in a time division manner. The maximum gate-cathode voltageVgk1 of the light emitting thyristor 211-1 and the maximum gate-cathodevoltage Vgk2 of the light emitting thyristor 212-1 are 3 V. In contrast,in the second embodiment, the maximum gate-cathode voltage Vgk1 of thelight emitting thyristor 212-1 and the maximum gate-cathode voltage Vgk2of the light emitting thyristor 211-1 are 4.4 V.

Referring to FIG. 26, the main scanning sync signal HD-HSYNC-N input tothe driver IC 100 rests the driver IC 100 so that the selection signalS1N goes high (High level) and the selection signal S2N goes low (Lowlevel). The selection signal S1N is input into the first gate driver 162shown in FIG. 22A and the selection signal S2N is input into the secondgate driver 163. Thus, the first gate driver 162 outputs the gate drivesignal G1 at the High level and the second gate driver 163 outputs thegate drive signal G2 at the Low level.

The drive signals G1 and G2 have an output voltage VoH equal to VDD-Vbewhere VDD is the supply voltage and Vbe is the base-emitter voltage ofthe NPN transistor 408, and an output voltage VoL equal to thegate-source voltage Vgs of the PMOS transistor 404.

The gate-source voltage Vgs is slightly higher than the thresholdvoltage Vt, and can be varied by adjusting a substrate bias voltageacross the source and the substrate, gate length, and gate width of thePMOS transistor 404. The following is a design example. When the supplyvoltage VDD=5 V, Vbe=0.6 V, and Vgs=2 V, the output voltage VoH=4.4 Vand VoL=2 V. These values are shown as exemplary values in FIG. 26.

When the latch signal LOAD is input into the driver IC 100 at time T1(at portion A in FIG. 26), the selection signal S1N goes low (Lowlevel), VoL, and the selection signal S2N goes high (High level), i.e.,VoH which in turn causes the gate-cathode voltage Vgk1 to decrease fromabout 4.4 V to about 2 V as depicted at portion C, and the gate-cathodevoltage Vgk2 to increase from about 2 V to about 4.4 V.

At time T2, the print drive signal STB-N goes low (Low level) asdepicted at portion E, causing the anode current Ia of the thyristor 212to rise as depicted at portion F. As described with respect to FIG. 21B,when the light emitting thyristor 212-1 begins to turn on, a part of theanode current Ia injected into the light emitting thyristor 212-1 willflow out as a gate current Ig from the gate of the light emittingthyristor 212-1, thereby turning on the light emitting thyristor 212-1.

The hatched portion of the anode current Ia (portion H) becomes a gatecurrent Ig1 (portion G). The gate current Ig1 flows into the gate driver162 shown in FIG. 22A so that the output voltage of the gate driver 162increases slightly (portion I). As the light emitting thyristor 212-1turns on, the gate-cathode voltage Vgk1 decreases to about 0.2 V(portion K). The gate-cathode voltage Vgk1 equal to 0.2 V issubstantially equal to the emitter-collector saturation voltage Vce(sat)of the NPN transistor 222 shown in FIG. 21E.

The gate current Ig causes the light emitting thyristor 212-1 shown inFIG. 22A to turn on to emit light. However, the gate-cathode voltageVgk2 of the light emitting thyristor 211-1 is about 4.4 V which is theHigh level so that the gate current Ig2 will not flow from anode to gateand therefore the light emitting thyristor 211-1 remains de-energized.

At time T3, the print drive signal STB-N goes high (High level) asdepicted at the portion L, causing the anode current Ia to decrease asdepicted at portion M. When the anode current Ia has decreased below theholding current of the light emitting thyristor 212, the light emittingthyristor begins to turn off and the anode voltage begins to increase.The anode voltage causes the gate current Ig1 to flow as depicted at theportion N. The gate Ig1 is a part of the anode current Ia andcorresponds to the hatched portion O of the anode current Ia. As thegate current Ig1 depicted at portion N decreases, the light emittingthyristor 212 will enter its OFF region so that the gate-cathode voltageVgk1 will increase to about 2 V (portion P) which is the Low leveloutput voltage VoL of the gate driver 162.

At time T4, the latch signal LOAD as depicted at portion Q is input intothe driver IC 100, causing the first selection signal S1N to go high(High level) and the second selection signal S2N to go low (Low level)as depicted at portion R. Thus, the gate drive signal G1 goes high (Highlevel) and the gate drive signal G2 goes low (Low level). As describedabove, the High level output voltage VoH of the gate driver 162 is about4.4 V as depicted at portion S and will not increase to the supplyvoltage VDD. Meanwhile, the gate-cathode voltage Vgk2 will decrease toabout 2 V as depicted at portion T.

At time T5, the print drive signal STB-N as depicted at portion U goeslow (Low level), causing the anode current Ia to begin to flow again asdepicted at portion V. As described with reference to FIG. 21A, when thelight emitting thyristor 211-1 begins to turn on, a part of the anodecurrent Ia flows out of the gate as the gate current Ig2, causing thelight emitting thyristor 211-1 to enter its ON state.

A hatched portion of the anode current Ia denoted by X corresponds tothe gate current Ig2 of the light emitting thyristor 211-1 as depictedat portion W. The gate current Ig2 flows into the output terminals ofthe gate driver 163 to cause the output voltage of the gate driver 163to increase slightly as depicted at portion Y. The output voltage ofthe-gate driver 163 will then decrease to about 0.2 V (portion Z) as thelight emitting thyristor 211-1 enters its ON state. This voltage of 0.2V corresponds to the collector-emitter saturation voltage Vce(sat) ofthe NPN transistor 222 described with reference to FIG. 21B.

The gate current Ig2 causes the light emitting thyristor 211-1 to turnon to emit light. Meanwhile, the gate-cathode voltage Vgk1 of the lightemitting thyristor 212 is about 4.4 V which is the High level, and nogate current Ig1 flows from anode to gate. Thus, the light emittingthyristor 212-1 remains off. At time T6, the print drive signal STB-Ngoes high (High level), causing the anode current Ia of the lightemitting thyristor 211-1 to decrease.

In this manner, the light emitting thyristors 212-1 and 211-1 shown inFIG. 22A are alternately switched between the ON state and the OFF statesuch that the High level of G1 and G2 causes the light emittingthyristors 212 and 211 to turn on. The gate drive signals G1 and G2being in opposite levels. For example, the falling edge of the printdrive signal STB-N at portion E causes the thyristors 212-1, 212-2, . .. to turn on and the thyristors 211-1, 211-2, . . . to turn off, and thefalling edge at portion U causes the thyristors 211-1, 211-2, . . . toturn on and the thyristors 212-1, 212-2, . . . to turn off.

As described above, when the anode current Ia flows, the Light emittingthyristors 211-1 and 212-1 turn on, the light output being determined bythe anode current Ia. The anode current Ia can be shut off by settingthe print data signals HD-DATA3 to HD-DATA0 (portions U and V) shown inFIG. 16) to the OFF state, thereby turning off the light emittingthyristors 211-1 and 212-1.

Modification 1 to Second Embodiment

FIG. 27 is a schematic diagram illustrating a modification to the gatedriver 162D shown in FIG. 25. Elements similar to those shown in FIGS.23 and 25 have been given the common reference numerals.

The gate driver 162E differs from the gate driver 162B (FIG. 23) in thata diode 409 is used in place of the PMOS transistor 406. The diode 409serves to set the High level output voltage VoH to a value lower thanVDD.

The input terminal IN is connected to the gate of a first switchingelement, e.g., PMOS transistor 403 via the inverter 401 and the timingadjusting circuit 405. The diode 409 has its anode connected to the VDDterminal and its cathode connected to the output terminal OUT throughthe PMOS transistor 403. The output node N401 of the inverter 401 isconnected to the gate of the second switching element, e.g., PMOStransistor 404 via the inverter 402. The output terminal OUT isconnected to the ground GND through the PMOS transistor 404.

The timing adjusting circuit 405 is an analog switch that includes anNMOS 405 a and a PMOS 405 b. The timing adjusting circuit 405 isemployed for the purpose of delaying the signal fed to the PMOStransistor 403 by an amount of time substantially equal to the delaytime of the inverter 402, so that the PMOS transistor 403 turns onsubstantially at the same that the PMOS transistor 404 turns off, and sothat the PMOS transistor 403 turns off substantially at the same thatthe PMOS transistor 404 turns on. This prevents malfunction of the gatedriver 162E due to a crowbar current from the supply voltage terminalVDD to the ground GND. The remaining configuration is the same as thoseshown in FIGS. 14B and 23.

The operation of the gate driver 162E shown in FIG. 27 will bedescribed. When the input terminal IN of the gate driver 162E is at theLow level (about 0 V), the output node N401 of the inverter 401 is atthe High level (about 5 V) and the output node N402 of the inverter 402is at the Low level (about 0 V). At this moment, the PMOS transistor 403is OFF and the PMOS transistor 404 is ON so that the voltage at theoutput terminal OUT decreases to the Low level, i.e., output voltageVoL. The output voltage VoL corresponds to the gate-source voltage Vgsof the PMOS transistor 404 which in turn is determined by the thresholdvoltage Vt, typically 2 V.

When the input terminal IN of the gate driver 162E is at the High level(about 5 V), the output terminals node N401 of the inverter 401 is atthe Low level (about 0 V), and the output terminal node N402 of theinverter 402 is at the High level (about 5V). At this moment, the PMOStransistor 404 becomes OFF while the PMOS transistor 403 becomes ON,causing the voltage at the output terminal OUT to rise to the High leveloutput voltage VoH. The output voltage VoH is equal to VDD-Vf where Vfis the forward voltage of the diode 409 which is typically 0.6 V. Thus,the output voltage VoH is about 4.4 V.

Modification 2 to Second Embodiment

FIG. 28 is a schematic diagram of the gate driver 162F which is amodification to the gate driver 162D (FIG. 25). Elements common to thegate driver 162E shown in FIG. 27 have been given like referencenumerals.

The gate driver 162F employs the diode 409 of modification 1, whichserves to set the output voltage VoH lower than the supply voltage VDD,the diode 409 being positioned on a side of the PMOS transistor 403opposite the supply voltage terminal VDD.

In other words, the PMOS transistor 403 has its source connected to thesupply voltage terminal VDD and its drain connected to the anode of thediode 409. The cathode of the diode 409 is connected to the outputterminal OUT. The PMOS transistor 404 has its source connected to theoutput terminal OUT and its drain connected to the ground GND. Theremaining configuration is the same as that of modification 1.

The operation of the gate driver 162F shown in FIG. 28 will bedescribed. When the input terminal IN of the gate driver 162F is at theLow level (about 0 V), the output node N401 of the inverter 401 is atthe High level (about 5 V), and the output node N402 of the inverter 402is at the Low level (about 0 V). At this moment, the PMOS transistor 403becomes OFF and the PMOS transistor 404 becomes ON, causing the voltageat the output terminal OUT to decrease to the Low level, i.e., VoL. Theoutput voltage VoL is substantially equal to the gate-source voltageVgs. The gate-source voltage Vgs is determined by the threshold voltageVt, typically 2 V.

When the input terminal IN of the gate driver 162F is at the High level(about 5 V), the output node N401 of the inverter 401 is at the Lowlevel (about 0 V) and the output node N402 of the inverter 402 is at theHigh level (about 5 V). At this moment, the PMOS transistor 404 becomesOFF and the PMOS transistor 403 becomes ON, causing the output voltageat the output terminal OUT to increase to the High level output voltageVoH. The output voltage VoH is equal to VDD-Vf where VDD is the supplyvoltage and Vf is the forward voltage of the diode 409, typically about0.6 V. Thus, the High level output voltage VoH is about 4.4 V.

As described above, the gate drivers 162D, 162E, and 162F shown in FIG.25, FIG. 27, and FIG. 28, respectively, operate essentially the same wayas the gate driver 162 shown in FIG. 14B, that is, the Low level outputvoltage VoL is higher than 0 V and the High level output voltage VoH islower than 5 V which is the supply voltage VDD.

In this manner, once the light emitting thyristor 210 has turned on, thegate current Ig falls substantially zero. When the light emittingthyristor 210 is OFF, the gate-cathode voltage can be lower than thebreakdown voltage of the light emitting thyristor 210.

Effects of Second Embodiment

The combination of the optical print head 13 with the driver IC 100 thatemploys the gate driver 162D, 162E, 162F, or 163 provides the followingeffects.

The High level output of the gate drivers 162D, 162E, or and 162F islower than the supply voltage VDD (5V). Thus, the gate-cathode voltageof the light emitting thyristor 210 is lower than the breakdown voltageof the light emitting thyristor, eliminating the risk of the lightemitting thyristor 210 being damaged.

The image forming apparatus 1 according to the second embodiment andmodifications 1 and 2 to the second embodiment employ the optical printhead 13 that incorporates the driver IC 100, thereby offering imageforming apparatus, e.g., printers, copying machines, facsimile machines,and multi-function printers (MFPs) having high space efficiency andlight output efficiency. The use of the optical print head 13 may beapplicable not only to a full color image forming apparatus but also toan image forming apparatus that prints monochrome images or multicolorimages. The optical print head 13 is particularly suitable for a fullcolor image forming apparatus that uses a plurality of exposing units.

Other Modifications

The present invention is not limited to the first embodiment, the secondembodiment, and the modifications but may be further modified in avariety of ways.

While the present invention has been described in terms of the lightemitting thyristors as light emitting elements, the invention may alsobe applied to other elements such as LEDs, organic EL elements, and heatgenerating resistors that are driven by a controlled voltage. Forexample, the invention may be applied to a printer that employs anorganic EL print head incorporating an array of organic EL elements anda thermal printer that employs an array of heat generating resistors.The invention may also be applied to display elements arranged in a rowor in a matrix.

The present invention may be applied not only to three-terminal elementssuch as light emitting thyristors but also to four-terminal thyristorsor silicon semiconductor controlled switches (SCS) having a first gateand a second gate.

As is clear from the description of the embodiments of the invention,the application of the present invention may not be limited to thedriving of a row of elements but may be widely applied to IC chips inany shape having either a single drive terminal or a plurality of driveterminals or to a unit that incorporates such IC chips.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the scope of the invention, and all such modifications aswould be obvious to one skilled in the art are intended to be includedwithin the scope of the following claims.

1. A driver circuit for driving a plurality of groups of elements, eachelement including a first terminal, a second terminal connected to afirst node at a first potential, and a third terminal that controlselectrical conduction between the first terminal and the secondterminal, the driver circuit comprising: a first driver section forsimultaneously driving first terminals of the elements of the pluralityof groups of elements; a second driver section simultaneously drivingthird terminals of elements in a corresponding group of the plurality ofgroups; wherein the second driver section includes a series connectionof a first switch element and a voltage level shifter, the seriesconnection being connected between a second node at a second potentialand the group of third terminals, and the second driver section furtherincluding a second switch element connected between the third terminalsand the first node.
 2. The driver circuit according to claim 1, whereinthe second driver section further includes a timing adjusting circuitfor adjusting a timing at which the first switch element is switchedbetween an on-state and an off-state.
 3. The driver circuit according toclaim 2, wherein the timing adjusting circuit operates such that thefirst switch element and the second switch element are switched betweenan on-state and an-off state substantially simultaneously.
 4. The drivercircuit according to claim 1, wherein the voltage level shifter is on aside of the first switch element opposite the group of third terminals.5. The driver circuit according to claim 1, wherein the first switchelement is on a side of the voltage level shifter opposite the group ofthird terminals.
 6. The driver circuit according to claim 1, wherein thefirst switch element, the second switch element, and the voltage shifterare formed of transistors of a common conductivity type.
 7. A drivercircuit for driving a plurality of groups of elements, each elementincluding a first terminal, a second terminal connected to a first nodeat a first potential, and a third terminal that controls electricalconduction between the first terminal and the second terminal, thedriver circuit comprising: a first driver section for simultaneouslydriving first terminals of the elements of the plurality of groups ofelements; a second driver section simultaneously driving third terminalsof elements in a corresponding group of the plurality of groups; whereinthe second driver section includes a first switch element connectedbetween a second node at a second potential and the third terminals ofelements in the corresponding group, and a second switch elementconnected between the third terminals of elements in the correspondinggroup and the first node, the second switch element being of a differentconductivity type from the first switch element.
 8. The driver circuitaccording to claim 7, wherein the first switch element and the secondswitch element are formed of a voltage-controlled transistor.
 9. Thedriver circuit according to claim 7, wherein the first switch element isformed of a current-controlled transistor and the second switch elementis formed of a voltage-controlled transistor.
 10. A driver circuit fordriving a plurality of groups of elements, each element including afirst terminal, a second terminal connected to a first node at a firstpotential, and a third terminal that controls electrical conductionbetween the first terminal and the second terminal, the driver circuitcomprising: a first driver section for simultaneously driving firstterminals of the elements of the plurality of groups of elements; asecond driver section simultaneously driving third terminals of elementsin a corresponding group of the plurality of groups; wherein the seconddriver section includes a series connection of a first switch elementand a forward-biased diode, the series circuit being connected between asecond node at a second potential and the group of third terminals, thesecond driver section further including a second switch elementconnected between the third terminals and the first node, the secondswitch element being of a common conductivity type to the first switchelement.
 11. The driver circuit according to claim 10, wherein thesecond driver section further includes a timing adjusting circuit foradjusting a timing at which the first switch element is switched betweenits on state and off state.
 12. The driver circuit according to claim11, wherein the timing adjusting circuit operates such that the firstswitch element and the second switch element are switched between anon-state and an off-state substantially simultaneously.
 13. The drivercircuit according to claim 10, wherein the first switch element is on aside of the diode opposite the second node.
 14. The driver circuitaccording to claim 10, wherein the diode is on a side of the firstswitch element opposite the second node.
 15. The driver circuitaccording to claim 1, wherein the first node is the ground.
 16. Thedriver circuit according to claim 1, wherein the first driver sectiondrives first current flowing through the first terminals, and the seconddriver section drives second current flowing through the third terminalsof elements in a corresponding group of the plurality of groups, thesecond current being at least a portion of the first current.
 17. Adriver apparatus comprising a driver circuit according to claim 1 and anarray of elements driven by the driver circuit.
 18. An image formingapparatus comprising a driver apparatus according to claim 17.